platforms/powernv/pci-sriov.c

149 	struct pnv_iov_data *iov;
152 	iov = kzalloc(sizeof(*iov), GFP_KERNEL);
153 	if (!iov)
155 	pdev->dev.archdata.iov_data = iov;
194 			iov->m64_single_mode[i] = true;
209 		iov->need_shift = true;
223 	kfree(iov);
252 	struct pnv_iov_data *iov = pnv_iov_get(pdev);
255 	 * iov can be null if we have an SR-IOV device with IOV BAR that can't
260 	if (!iov)
268 	if (iov->m64_single_mode[resno - PCI_IOV_RESOURCES])
286 	struct pnv_iov_data   *iov;
291 	iov = pnv_iov_get(pdev);
293 	for_each_set_bit(window_id, iov->used_m64_bar_mask, MAX_M64_BARS) {
398 static int pnv_pci_alloc_m64_bar(struct pnv_phb *phb, struct pnv_iov_data *iov)
410 	set_bit(win, iov->used_m64_bar_mask);
417 	struct pnv_iov_data   *iov;
427 	iov = pnv_iov_get(pdev);
435 		if (!iov->m64_single_mode[i]) {
436 			win = pnv_pci_alloc_m64_bar(phb, iov);
452 		base_pe_num = iov->vf_pe_arr[0].pe_number;
455 			win = pnv_pci_alloc_m64_bar(phb, iov);
506 	struct pnv_iov_data *iov;
513 	iov = pnv_iov_get(dev);
523 	num_vfs = iov->num_vfs;
528 		if (iov->m64_single_mode[i])
561 		if (iov->m64_single_mode[i])
573 			devm_release_resource(&dev->dev, &iov->holes[i]);
574 			memset(&iov->holes[i], 0, sizeof(iov->holes[i]));
580 			iov->holes[i].start = res2.start;
581 			iov->holes[i].end = res2.start + size * offset - 1;
582 			iov->holes[i].flags = IORESOURCE_BUS;
583 			iov->holes[i].name = "pnv_iov_reserved";
585 					&iov->holes[i]);
594 	struct pnv_iov_data   *iov;
596 	iov = pnv_iov_get(pdev);
597 	if (WARN_ON(!iov))
600 	num_vfs = iov->num_vfs;
601 	base_pe = iov->vf_pe_arr[0].pe_number;
607 	if (iov->need_shift)
620 	struct pnv_iov_data   *iov;
628 	iov = pnv_iov_get(pdev);
636 		pe = &iov->vf_pe_arr[vf_index];
677 	struct pnv_iov_data   *iov;
683 	iov = pnv_iov_get(pdev);
697 	if (!iov) {
709 	iov->vf_pe_arr = base_pe;
710 	iov->num_vfs = num_vfs;
724 	if (iov->need_shift) {
740 		pnv_ioda_free_pe(&iov->vf_pe_arr[i]);