Lines Matching refs:csa
81 static inline int check_spu_isolate(struct spu_state *csa, struct spu *spu)
97 static inline void disable_interrupts(struct spu_state *csa, struct spu *spu)
111 if (csa) {
112 csa->priv1.int_mask_class0_RW = spu_int_mask_get(spu, 0);
113 csa->priv1.int_mask_class1_RW = spu_int_mask_get(spu, 1);
114 csa->priv1.int_mask_class2_RW = spu_int_mask_get(spu, 2);
134 static inline void set_watchdog_timer(struct spu_state *csa, struct spu *spu)
147 static inline void inhibit_user_access(struct spu_state *csa, struct spu *spu)
158 static inline void set_switch_pending(struct spu_state *csa, struct spu *spu)
167 static inline void save_mfc_cntl(struct spu_state *csa, struct spu *spu)
182 if (csa)
183 csa->priv2.mfc_control_RW =
192 if (csa)
193 csa->priv2.mfc_control_RW =
201 static inline void save_spu_runcntl(struct spu_state *csa, struct spu *spu)
209 csa->prob.spu_runcntl_RW = in_be32(&prob->spu_runcntl_RW);
212 static inline void save_mfc_sr1(struct spu_state *csa, struct spu *spu)
217 csa->priv1.mfc_sr1_RW = spu_mfc_sr1_get(spu);
220 static inline void save_spu_status(struct spu_state *csa, struct spu *spu)
228 csa->prob.spu_status_R = in_be32(&prob->spu_status_R);
240 csa->prob.spu_status_R = SPU_STATUS_RUNNING;
242 csa->prob.spu_status_R = in_be32(&prob->spu_status_R);
246 static inline void save_mfc_stopped_status(struct spu_state *csa,
259 csa->priv2.mfc_control_RW &= ~mask;
260 csa->priv2.mfc_control_RW |= in_be64(&priv2->mfc_control_RW) & mask;
263 static inline void halt_mfc_decr(struct spu_state *csa, struct spu *spu)
276 static inline void save_timebase(struct spu_state *csa, struct spu *spu)
282 csa->suspend_time = get_cycles();
285 static inline void remove_other_spu_access(struct spu_state *csa,
294 static inline void do_mfc_mssync(struct spu_state *csa, struct spu *spu)
307 static inline void issue_mfc_tlbie(struct spu_state *csa, struct spu *spu)
319 static inline void handle_pending_interrupts(struct spu_state *csa,
333 static inline void save_mfc_queues(struct spu_state *csa, struct spu *spu)
344 csa->priv2.puq[i].mfc_cq_data0_RW =
346 csa->priv2.puq[i].mfc_cq_data1_RW =
348 csa->priv2.puq[i].mfc_cq_data2_RW =
350 csa->priv2.puq[i].mfc_cq_data3_RW =
354 csa->priv2.spuq[i].mfc_cq_data0_RW =
356 csa->priv2.spuq[i].mfc_cq_data1_RW =
358 csa->priv2.spuq[i].mfc_cq_data2_RW =
360 csa->priv2.spuq[i].mfc_cq_data3_RW =
366 static inline void save_ppu_querymask(struct spu_state *csa, struct spu *spu)
374 csa->prob.dma_querymask_RW = in_be32(&prob->dma_querymask_RW);
377 static inline void save_ppu_querytype(struct spu_state *csa, struct spu *spu)
385 csa->prob.dma_querytype_RW = in_be32(&prob->dma_querytype_RW);
388 static inline void save_ppu_tagstatus(struct spu_state *csa, struct spu *spu)
398 csa->prob.dma_tagstatus_R = in_be32(&prob->dma_tagstatus_R);
401 static inline void save_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)
409 csa->priv2.spu_tag_status_query_RW =
413 static inline void save_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)
421 csa->priv2.spu_cmd_buf1_RW = in_be64(&priv2->spu_cmd_buf1_RW);
422 csa->priv2.spu_cmd_buf2_RW = in_be64(&priv2->spu_cmd_buf2_RW);
425 static inline void save_mfc_csr_ato(struct spu_state *csa, struct spu *spu)
433 csa->priv2.spu_atomic_status_RW = in_be64(&priv2->spu_atomic_status_RW);
436 static inline void save_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
442 csa->priv1.mfc_tclass_id_RW = spu_mfc_tclass_id_get(spu);
445 static inline void set_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
456 static inline void purge_mfc_queue(struct spu_state *csa, struct spu *spu)
470 static inline void wait_purge_complete(struct spu_state *csa, struct spu *spu)
483 static inline void setup_mfc_sr1(struct spu_state *csa, struct spu *spu)
501 static inline void save_spu_npc(struct spu_state *csa, struct spu *spu)
508 csa->prob.spu_npc_RW = in_be32(&prob->spu_npc_RW);
511 static inline void save_spu_privcntl(struct spu_state *csa, struct spu *spu)
518 csa->priv2.spu_privcntl_RW = in_be64(&priv2->spu_privcntl_RW);
521 static inline void reset_spu_privcntl(struct spu_state *csa, struct spu *spu)
533 static inline void save_spu_lslr(struct spu_state *csa, struct spu *spu)
540 csa->priv2.spu_lslr_RW = in_be64(&priv2->spu_lslr_RW);
543 static inline void reset_spu_lslr(struct spu_state *csa, struct spu *spu)
555 static inline void save_spu_cfg(struct spu_state *csa, struct spu *spu)
562 csa->priv2.spu_cfg_RW = in_be64(&priv2->spu_cfg_RW);
565 static inline void save_pm_trace(struct spu_state *csa, struct spu *spu)
573 static inline void save_mfc_rag(struct spu_state *csa, struct spu *spu)
579 csa->priv1.resource_allocation_groupID_RW =
581 csa->priv1.resource_allocation_enable_RW =
585 static inline void save_ppu_mb_stat(struct spu_state *csa, struct spu *spu)
592 csa->prob.mb_stat_R = in_be32(&prob->mb_stat_R);
595 static inline void save_ppu_mb(struct spu_state *csa, struct spu *spu)
602 csa->prob.pu_mb_R = in_be32(&prob->pu_mb_R);
605 static inline void save_ppuint_mb(struct spu_state *csa, struct spu *spu)
612 csa->priv2.puint_mb_R = in_be64(&priv2->puint_mb_R);
615 static inline void save_ch_part1(struct spu_state *csa, struct spu *spu)
626 csa->spu_chnldata_RW[1] = in_be64(&priv2->spu_chnldata_RW);
633 csa->spu_chnldata_RW[idx] = in_be64(&priv2->spu_chnldata_RW);
634 csa->spu_chnlcnt_RW[idx] = in_be64(&priv2->spu_chnlcnt_RW);
641 static inline void save_spu_mb(struct spu_state *csa, struct spu *spu)
651 csa->spu_chnlcnt_RW[29] = in_be64(&priv2->spu_chnlcnt_RW);
653 csa->spu_mailbox_data[i] = in_be64(&priv2->spu_chnldata_RW);
659 static inline void save_mfc_cmd(struct spu_state *csa, struct spu *spu)
668 csa->spu_chnlcnt_RW[21] = in_be64(&priv2->spu_chnlcnt_RW);
672 static inline void reset_ch(struct spu_state *csa, struct spu *spu)
692 static inline void resume_mfc_queue(struct spu_state *csa, struct spu *spu)
703 static inline void setup_mfc_slbs(struct spu_state *csa, struct spu *spu,
721 spu_setup_kernel_slbs(spu, csa->lscsa, code, code_size);
724 static inline void set_switch_active(struct spu_state *csa, struct spu *spu)
732 * Now that we have saved the mfc in the csa, we can add in the
736 csa->priv2.mfc_control_RW |= MFC_CNTL_RESTART_DMA_COMMAND;
741 static inline void enable_interrupts(struct spu_state *csa, struct spu *spu)
798 static inline void save_ls_16kb(struct spu_state *csa, struct spu *spu)
800 unsigned long addr = (unsigned long)&csa->lscsa->ls[0];
814 static inline void set_spu_npc(struct spu_state *csa, struct spu *spu)
831 static inline void set_signot1(struct spu_state *csa, struct spu *spu)
844 addr64.ull = (u64) csa->lscsa;
849 static inline void set_signot2(struct spu_state *csa, struct spu *spu)
862 addr64.ull = (u64) csa->lscsa;
867 static inline void send_save_code(struct spu_state *csa, struct spu *spu)
883 static inline void set_ppu_querymask(struct spu_state *csa, struct spu *spu)
896 static inline void wait_tag_complete(struct spu_state *csa, struct spu *spu)
919 static inline void wait_spu_stopped(struct spu_state *csa, struct spu *spu)
938 static inline int check_save_status(struct spu_state *csa, struct spu *spu)
953 static inline void terminate_spu_app(struct spu_state *csa, struct spu *spu)
961 static inline void suspend_mfc_and_halt_decr(struct spu_state *csa,
975 static inline void wait_suspend_mfc_complete(struct spu_state *csa,
989 static inline int suspend_spe(struct spu_state *csa, struct spu *spu)
1031 static inline void clear_spu_status(struct spu_state *csa, struct spu *spu)
1065 static inline void reset_ch_part1(struct spu_state *csa, struct spu *spu)
1090 static inline void reset_ch_part2(struct spu_state *csa, struct spu *spu)
1110 static inline void setup_spu_status_part1(struct spu_state *csa,
1136 (csa->prob.spu_status_R >> SPU_STOP_STATUS_SHIFT) & 0xFFFF;
1137 if ((csa->prob.spu_status_R & status_P_I) == status_P_I) {
1143 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_I;
1144 csa->lscsa->stopped_status.slot[1] = status_code;
1146 } else if ((csa->prob.spu_status_R & status_P_H) == status_P_H) {
1152 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_H;
1153 csa->lscsa->stopped_status.slot[1] = status_code;
1155 } else if ((csa->prob.spu_status_R & status_S_P) == status_S_P) {
1160 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_P;
1161 csa->lscsa->stopped_status.slot[1] = status_code;
1163 } else if ((csa->prob.spu_status_R & status_S_I) == status_S_I) {
1168 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_I;
1169 csa->lscsa->stopped_status.slot[1] = status_code;
1171 } else if ((csa->prob.spu_status_R & status_P) == status_P) {
1176 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P;
1177 csa->lscsa->stopped_status.slot[1] = status_code;
1179 } else if ((csa->prob.spu_status_R & status_H) == status_H) {
1184 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_H;
1186 } else if ((csa->prob.spu_status_R & status_S) == status_S) {
1190 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S;
1192 } else if ((csa->prob.spu_status_R & status_I) == status_I) {
1197 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_I;
1202 static inline void setup_spu_status_part2(struct spu_state *csa,
1221 if (!(csa->prob.spu_status_R & mask)) {
1222 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_R;
1226 static inline void restore_mfc_rag(struct spu_state *csa, struct spu *spu)
1233 csa->priv1.resource_allocation_groupID_RW);
1235 csa->priv1.resource_allocation_enable_RW);
1238 static inline void send_restore_code(struct spu_state *csa, struct spu *spu)
1254 static inline void setup_decr(struct spu_state *csa, struct spu *spu)
1263 if (csa->priv2.mfc_control_RW & MFC_CNTL_DECREMENTER_RUNNING) {
1265 cycles_t delta_time = resume_time - csa->suspend_time;
1267 csa->lscsa->decr_status.slot[0] = SPU_DECR_STATUS_RUNNING;
1268 if (csa->lscsa->decr.slot[0] < delta_time) {
1269 csa->lscsa->decr_status.slot[0] |=
1273 csa->lscsa->decr.slot[0] -= delta_time;
1275 csa->lscsa->decr_status.slot[0] = 0;
1279 static inline void setup_ppu_mb(struct spu_state *csa, struct spu *spu)
1284 csa->lscsa->ppu_mb.slot[0] = csa->prob.pu_mb_R;
1287 static inline void setup_ppuint_mb(struct spu_state *csa, struct spu *spu)
1292 csa->lscsa->ppuint_mb.slot[0] = csa->priv2.puint_mb_R;
1295 static inline int check_restore_status(struct spu_state *csa, struct spu *spu)
1310 static inline void restore_spu_privcntl(struct spu_state *csa, struct spu *spu)
1317 out_be64(&priv2->spu_privcntl_RW, csa->priv2.spu_privcntl_RW);
1321 static inline void restore_status_part1(struct spu_state *csa, struct spu *spu)
1333 if (csa->prob.spu_status_R & mask) {
1341 static inline void restore_status_part2(struct spu_state *csa, struct spu *spu)
1356 if (!(csa->prob.spu_status_R & mask)) {
1368 static inline void restore_ls_16kb(struct spu_state *csa, struct spu *spu)
1370 unsigned long addr = (unsigned long)&csa->lscsa->ls[0];
1384 static inline void suspend_mfc(struct spu_state *csa, struct spu *spu)
1396 static inline void clear_interrupts(struct spu_state *csa, struct spu *spu)
1416 static inline void restore_mfc_queues(struct spu_state *csa, struct spu *spu)
1425 if ((csa->priv2.mfc_control_RW & MFC_CNTL_DMA_QUEUES_EMPTY_MASK) == 0) {
1428 csa->priv2.puq[i].mfc_cq_data0_RW);
1430 csa->priv2.puq[i].mfc_cq_data1_RW);
1432 csa->priv2.puq[i].mfc_cq_data2_RW);
1434 csa->priv2.puq[i].mfc_cq_data3_RW);
1438 csa->priv2.spuq[i].mfc_cq_data0_RW);
1440 csa->priv2.spuq[i].mfc_cq_data1_RW);
1442 csa->priv2.spuq[i].mfc_cq_data2_RW);
1444 csa->priv2.spuq[i].mfc_cq_data3_RW);
1450 static inline void restore_ppu_querymask(struct spu_state *csa, struct spu *spu)
1457 out_be32(&prob->dma_querymask_RW, csa->prob.dma_querymask_RW);
1461 static inline void restore_ppu_querytype(struct spu_state *csa, struct spu *spu)
1468 out_be32(&prob->dma_querytype_RW, csa->prob.dma_querytype_RW);
1472 static inline void restore_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)
1480 csa->priv2.spu_tag_status_query_RW);
1484 static inline void restore_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)
1492 out_be64(&priv2->spu_cmd_buf1_RW, csa->priv2.spu_cmd_buf1_RW);
1493 out_be64(&priv2->spu_cmd_buf2_RW, csa->priv2.spu_cmd_buf2_RW);
1497 static inline void restore_mfc_csr_ato(struct spu_state *csa, struct spu *spu)
1504 out_be64(&priv2->spu_atomic_status_RW, csa->priv2.spu_atomic_status_RW);
1507 static inline void restore_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
1512 spu_mfc_tclass_id_set(spu, csa->priv1.mfc_tclass_id_RW);
1516 static inline void set_llr_event(struct spu_state *csa, struct spu *spu)
1529 ch0_cnt = csa->spu_chnlcnt_RW[0];
1530 ch0_data = csa->spu_chnldata_RW[0];
1531 ch1_data = csa->spu_chnldata_RW[1];
1532 csa->spu_chnldata_RW[0] |= MFC_LLR_LOST_EVENT;
1535 csa->spu_chnlcnt_RW[0] = 1;
1539 static inline void restore_decr_wrapped(struct spu_state *csa, struct spu *spu)
1546 if (!(csa->lscsa->decr_status.slot[0] & SPU_DECR_STATUS_WRAPPED))
1549 if ((csa->spu_chnlcnt_RW[0] == 0) &&
1550 (csa->spu_chnldata_RW[1] & 0x20) &&
1551 !(csa->spu_chnldata_RW[0] & 0x20))
1552 csa->spu_chnlcnt_RW[0] = 1;
1554 csa->spu_chnldata_RW[0] |= 0x20;
1557 static inline void restore_ch_part1(struct spu_state *csa, struct spu *spu)
1570 out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[idx]);
1571 out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[idx]);
1576 static inline void restore_ch_part2(struct spu_state *csa, struct spu *spu)
1588 ch_counts[1] = csa->spu_chnlcnt_RW[21];
1599 static inline void restore_spu_lslr(struct spu_state *csa, struct spu *spu)
1606 out_be64(&priv2->spu_lslr_RW, csa->priv2.spu_lslr_RW);
1610 static inline void restore_spu_cfg(struct spu_state *csa, struct spu *spu)
1617 out_be64(&priv2->spu_cfg_RW, csa->priv2.spu_cfg_RW);
1621 static inline void restore_pm_trace(struct spu_state *csa, struct spu *spu)
1629 static inline void restore_spu_npc(struct spu_state *csa, struct spu *spu)
1636 out_be32(&prob->spu_npc_RW, csa->prob.spu_npc_RW);
1640 static inline void restore_spu_mb(struct spu_state *csa, struct spu *spu)
1650 out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[29]);
1652 out_be64(&priv2->spu_chnldata_RW, csa->spu_mailbox_data[i]);
1657 static inline void check_ppu_mb_stat(struct spu_state *csa, struct spu *spu)
1665 if ((csa->prob.mb_stat_R & 0xFF) == 0) {
1671 static inline void check_ppuint_mb_stat(struct spu_state *csa, struct spu *spu)
1679 if ((csa->prob.mb_stat_R & 0xFF0000) == 0) {
1687 static inline void restore_mfc_sr1(struct spu_state *csa, struct spu *spu)
1692 spu_mfc_sr1_set(spu, csa->priv1.mfc_sr1_RW);
1696 static inline void set_int_route(struct spu_state *csa, struct spu *spu)
1703 static inline void restore_other_spu_access(struct spu_state *csa,
1711 static inline void restore_spu_runcntl(struct spu_state *csa, struct spu *spu)
1719 if (csa->prob.spu_status_R & SPU_STATUS_RUNNING) {
1725 static inline void restore_mfc_cntl(struct spu_state *csa, struct spu *spu)
1732 out_be64(&priv2->mfc_control_RW, csa->priv2.mfc_control_RW);
1738 * the csa, if the operational state was suspending or suspended. In
1745 static inline void enable_user_access(struct spu_state *csa, struct spu *spu)
1755 static inline void reset_switch_active(struct spu_state *csa, struct spu *spu)
1763 static inline void reenable_interrupts(struct spu_state *csa, struct spu *spu)
1769 spu_int_mask_set(spu, 0, csa->priv1.int_mask_class0_RW);
1770 spu_int_mask_set(spu, 1, csa->priv1.int_mask_class1_RW);
1771 spu_int_mask_set(spu, 2, csa->priv1.int_mask_class2_RW);
2133 static void init_prob(struct spu_state *csa)
2135 csa->spu_chnlcnt_RW[9] = 1;
2136 csa->spu_chnlcnt_RW[21] = 16;
2137 csa->spu_chnlcnt_RW[23] = 1;
2138 csa->spu_chnlcnt_RW[28] = 1;
2139 csa->spu_chnlcnt_RW[30] = 1;
2140 csa->prob.spu_runcntl_RW = SPU_RUNCNTL_STOP;
2141 csa->prob.mb_stat_R = 0x000400;
2144 static void init_priv1(struct spu_state *csa)
2147 csa->priv1.mfc_sr1_RW = MFC_STATE1_LOCAL_STORAGE_DECODE_MASK |
2153 csa->priv1.int_mask_class0_RW = CLASS0_ENABLE_DMA_ALIGNMENT_INTR |
2156 csa->priv1.int_mask_class1_RW = CLASS1_ENABLE_SEGMENT_FAULT_INTR |
2158 csa->priv1.int_mask_class2_RW = CLASS2_ENABLE_SPU_STOP_INTR |
2163 static void init_priv2(struct spu_state *csa)
2165 csa->priv2.spu_lslr_RW = LS_ADDR_MASK;
2166 csa->priv2.mfc_control_RW = MFC_CNTL_RESUME_DMA_QUEUE |
2182 int spu_init_csa(struct spu_state *csa)
2186 if (!csa)
2188 memset(csa, 0, sizeof(struct spu_state));
2190 rc = spu_alloc_lscsa(csa);
2194 spin_lock_init(&csa->register_lock);
2196 init_prob(csa);
2197 init_priv1(csa);
2198 init_priv2(csa);
2203 void spu_fini_csa(struct spu_state *csa)
2205 spu_free_lscsa(csa);