cell/spufs/hw_ops.c

18 #include <asm/spu.h>
26 	struct spu *spu = ctx->spu;
27 	struct spu_problem __iomem *prob = spu->problem;
31 	spin_lock_irq(&spu->register_lock);
37 	spin_unlock_irq(&spu->register_lock);
43 	return in_be32(&ctx->spu->problem->mb_stat_R);
48 	struct spu *spu = ctx->spu;
52 	spin_lock_irq(&spu->register_lock);
53 	stat = in_be32(&spu->problem->mb_stat_R);
64 			spu_int_stat_clear(spu, 2, CLASS2_MAILBOX_INTR);
65 			spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);
72 			spu_int_stat_clear(spu, 2,
74 			spu_int_mask_or(spu, 2,
78 	spin_unlock_irq(&spu->register_lock);
84 	struct spu *spu = ctx->spu;
85 	struct spu_problem __iomem *prob = spu->problem;
86 	struct spu_priv2 __iomem *priv2 = spu->priv2;
89 	spin_lock_irq(&spu->register_lock);
96 		spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);
99 	spin_unlock_irq(&spu->register_lock);
105 	struct spu *spu = ctx->spu;
106 	struct spu_problem __iomem *prob = spu->problem;
109 	spin_lock_irq(&spu->register_lock);
117 		spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR);
120 	spin_unlock_irq(&spu->register_lock);
126 	out_be32(&ctx->spu->problem->signal_notify1, data);
131 	out_be32(&ctx->spu->problem->signal_notify2, data);
136 	struct spu *spu = ctx->spu;
137 	struct spu_priv2 __iomem *priv2 = spu->priv2;
140 	spin_lock_irq(&spu->register_lock);
147 	spin_unlock_irq(&spu->register_lock);
152 	return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 1) != 0);
157 	struct spu *spu = ctx->spu;
158 	struct spu_priv2 __iomem *priv2 = spu->priv2;
161 	spin_lock_irq(&spu->register_lock);
168 	spin_unlock_irq(&spu->register_lock);
173 	return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 2) != 0);
178 	return in_be32(&ctx->spu->problem->spu_npc_RW);
183 	out_be32(&ctx->spu->problem->spu_npc_RW, val);
188 	return in_be32(&ctx->spu->problem->spu_status_R);
193 	return ctx->spu->local_store;
198 	out_be64(&ctx->spu->priv2->spu_privcntl_RW, val);
203 	return in_be32(&ctx->spu->problem->spu_runcntl_RW);
208 	spin_lock_irq(&ctx->spu->register_lock);
212 	out_be32(&ctx->spu->problem->spu_runcntl_RW, val);
213 	spin_unlock_irq(&ctx->spu->register_lock);
218 	spin_lock_irq(&ctx->spu->register_lock);
219 	out_be32(&ctx->spu->problem->spu_runcntl_RW, SPU_RUNCNTL_STOP);
220 	while (in_be32(&ctx->spu->problem->spu_status_R) & SPU_STATUS_RUNNING)
222 	spin_unlock_irq(&ctx->spu->register_lock);
227 	struct spu *spu = ctx->spu;
230 	spin_lock_irq(&spu->register_lock);
231 	sr1 = spu_mfc_sr1_get(spu) | MFC_STATE1_MASTER_RUN_CONTROL_MASK;
232 	spu_mfc_sr1_set(spu, sr1);
233 	spin_unlock_irq(&spu->register_lock);
238 	struct spu *spu = ctx->spu;
241 	spin_lock_irq(&spu->register_lock);
242 	sr1 = spu_mfc_sr1_get(spu) & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
243 	spu_mfc_sr1_set(spu, sr1);
244 	spin_unlock_irq(&spu->register_lock);
249 	struct spu_problem __iomem *prob = ctx->spu->problem;
252 	spin_lock_irq(&ctx->spu->register_lock);
260 	spin_unlock_irq(&ctx->spu->register_lock);
266 	return in_be32(&ctx->spu->problem->dma_tagstatus_R);
271 	return in_be32(&ctx->spu->problem->dma_qstatus_R);
278 	struct spu_problem __iomem *prob = ctx->spu->problem;
280 	spin_lock_irq(&ctx->spu->register_lock);
288 	spin_unlock_irq(&ctx->spu->register_lock);
302 	struct spu_priv2 __iomem *priv2 = ctx->spu->priv2;
304 	if (!test_bit(SPU_CONTEXT_SWITCH_PENDING, &ctx->spu->flags))