cell/spufs/backing_ops.c

40 	ch0_cnt = ctx->csa.spu_chnlcnt_RW[0];
41 	ch0_data = ctx->csa.spu_chnldata_RW[0];
42 	ch1_data = ctx->csa.spu_chnldata_RW[1];
43 	ctx->csa.spu_chnldata_RW[0] |= event;
45 		ctx->csa.spu_chnlcnt_RW[0] = 1;
54 	spin_lock(&ctx->csa.register_lock);
55 	mbox_stat = ctx->csa.prob.mb_stat_R;
61 		*data = ctx->csa.prob.pu_mb_R;
62 		ctx->csa.prob.mb_stat_R &= ~(0x0000ff);
63 		ctx->csa.spu_chnlcnt_RW[28] = 1;
67 	spin_unlock(&ctx->csa.register_lock);
73 	return ctx->csa.prob.mb_stat_R;
83 	spin_lock_irq(&ctx->csa.register_lock);
84 	stat = ctx->csa.prob.mb_stat_R;
95 			ctx->csa.priv1.int_stat_class2_RW &=
97 			ctx->csa.priv1.int_mask_class2_RW |=
105 			ctx->csa.priv1.int_stat_class2_RW &=
107 			ctx->csa.priv1.int_mask_class2_RW |=
111 	spin_unlock_irq(&ctx->csa.register_lock);
119 	spin_lock(&ctx->csa.register_lock);
120 	if (ctx->csa.prob.mb_stat_R & 0xff0000) {
125 		*data = ctx->csa.priv2.puint_mb_R;
126 		ctx->csa.prob.mb_stat_R &= ~(0xff0000);
127 		ctx->csa.spu_chnlcnt_RW[30] = 1;
132 		ctx->csa.priv1.int_mask_class2_RW |= CLASS2_ENABLE_MAILBOX_INTR;
135 	spin_unlock(&ctx->csa.register_lock);
143 	spin_lock(&ctx->csa.register_lock);
144 	if ((ctx->csa.prob.mb_stat_R) & 0x00ff00) {
145 		int slot = ctx->csa.spu_chnlcnt_RW[29];
146 		int avail = (ctx->csa.prob.mb_stat_R & 0x00ff00) >> 8;
153 		ctx->csa.spu_mailbox_data[slot] = data;
154 		ctx->csa.spu_chnlcnt_RW[29] = ++slot;
155 		ctx->csa.prob.mb_stat_R &= ~(0x00ff00);
156 		ctx->csa.prob.mb_stat_R |= (((4 - slot) & 0xff) << 8);
162 		ctx->csa.priv1.int_mask_class2_RW |=
166 	spin_unlock(&ctx->csa.register_lock);
172 	return ctx->csa.spu_chnldata_RW[3];
177 	spin_lock(&ctx->csa.register_lock);
178 	if (ctx->csa.priv2.spu_cfg_RW & 0x1)
179 		ctx->csa.spu_chnldata_RW[3] |= data;
181 		ctx->csa.spu_chnldata_RW[3] = data;
182 	ctx->csa.spu_chnlcnt_RW[3] = 1;
184 	spin_unlock(&ctx->csa.register_lock);
189 	return ctx->csa.spu_chnldata_RW[4];
194 	spin_lock(&ctx->csa.register_lock);
195 	if (ctx->csa.priv2.spu_cfg_RW & 0x2)
196 		ctx->csa.spu_chnldata_RW[4] |= data;
198 		ctx->csa.spu_chnldata_RW[4] = data;
199 	ctx->csa.spu_chnlcnt_RW[4] = 1;
201 	spin_unlock(&ctx->csa.register_lock);
208 	spin_lock(&ctx->csa.register_lock);
209 	tmp = ctx->csa.priv2.spu_cfg_RW;
214 	ctx->csa.priv2.spu_cfg_RW = tmp;
215 	spin_unlock(&ctx->csa.register_lock);
220 	return ((ctx->csa.priv2.spu_cfg_RW & 1) != 0);
227 	spin_lock(&ctx->csa.register_lock);
228 	tmp = ctx->csa.priv2.spu_cfg_RW;
233 	ctx->csa.priv2.spu_cfg_RW = tmp;
234 	spin_unlock(&ctx->csa.register_lock);
239 	return ((ctx->csa.priv2.spu_cfg_RW & 2) != 0);
244 	return ctx->csa.prob.spu_npc_RW;
249 	ctx->csa.prob.spu_npc_RW = val;
254 	return ctx->csa.prob.spu_status_R;
259 	return ctx->csa.lscsa->ls;
264 	ctx->csa.priv2.spu_privcntl_RW = val;
269 	return ctx->csa.prob.spu_runcntl_RW;
274 	spin_lock(&ctx->csa.register_lock);
275 	ctx->csa.prob.spu_runcntl_RW = val;
277 		ctx->csa.prob.spu_status_R &=
283 		ctx->csa.prob.spu_status_R |= SPU_STATUS_RUNNING;
285 		ctx->csa.prob.spu_status_R &= ~SPU_STATUS_RUNNING;
287 	spin_unlock(&ctx->csa.register_lock);
297 	struct spu_state *csa = &ctx->csa;
300 	spin_lock(&csa->register_lock);
301 	sr1 = csa->priv1.mfc_sr1_RW | MFC_STATE1_MASTER_RUN_CONTROL_MASK;
302 	csa->priv1.mfc_sr1_RW = sr1;
303 	spin_unlock(&csa->register_lock);
308 	struct spu_state *csa = &ctx->csa;
311 	spin_lock(&csa->register_lock);
312 	sr1 = csa->priv1.mfc_sr1_RW & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
313 	csa->priv1.mfc_sr1_RW = sr1;
314 	spin_unlock(&csa->register_lock);
320 	struct spu_problem_collapsed *prob = &ctx->csa.prob;
323 	spin_lock(&ctx->csa.register_lock);
336 	ctx->csa.prob.dma_tagstatus_R &= mask;
338 	spin_unlock(&ctx->csa.register_lock);
345 	return ctx->csa.prob.dma_tagstatus_R;
350 	return ctx->csa.prob.dma_qstatus_R;
358 	spin_lock(&ctx->csa.register_lock);
361 	spin_unlock(&ctx->csa.register_lock);
368 	ctx->csa.priv2.mfc_control_RW |= MFC_CNTL_RESTART_DMA_COMMAND;