cell/spufs/backing_ops.c

34 static void gen_spu_event(struct spu_context *ctx, u32 event)
40 	ch0_cnt = ctx->csa.spu_chnlcnt_RW[0];
41 	ch0_data = ctx->csa.spu_chnldata_RW[0];
42 	ch1_data = ctx->csa.spu_chnldata_RW[1];
43 	ctx->csa.spu_chnldata_RW[0] |= event;
45 		ctx->csa.spu_chnlcnt_RW[0] = 1;
49 static int spu_backing_mbox_read(struct spu_context *ctx, u32 * data)
54 	spin_lock(&ctx->csa.register_lock);
55 	mbox_stat = ctx->csa.prob.mb_stat_R;
61 		*data = ctx->csa.prob.pu_mb_R;
62 		ctx->csa.prob.mb_stat_R &= ~(0x0000ff);
63 		ctx->csa.spu_chnlcnt_RW[28] = 1;
64 		gen_spu_event(ctx, MFC_PU_MAILBOX_AVAILABLE_EVENT);
67 	spin_unlock(&ctx->csa.register_lock);
71 static u32 spu_backing_mbox_stat_read(struct spu_context *ctx)
73 	return ctx->csa.prob.mb_stat_R;
76 static __poll_t spu_backing_mbox_stat_poll(struct spu_context *ctx,
83 	spin_lock_irq(&ctx->csa.register_lock);
84 	stat = ctx->csa.prob.mb_stat_R;
95 			ctx->csa.priv1.int_stat_class2_RW &=
97 			ctx->csa.priv1.int_mask_class2_RW |=
105 			ctx->csa.priv1.int_stat_class2_RW &=
107 			ctx->csa.priv1.int_mask_class2_RW |=
111 	spin_unlock_irq(&ctx->csa.register_lock);
115 static int spu_backing_ibox_read(struct spu_context *ctx, u32 * data)
119 	spin_lock(&ctx->csa.register_lock);
120 	if (ctx->csa.prob.mb_stat_R & 0xff0000) {
125 		*data = ctx->csa.priv2.puint_mb_R;
126 		ctx->csa.prob.mb_stat_R &= ~(0xff0000);
127 		ctx->csa.spu_chnlcnt_RW[30] = 1;
128 		gen_spu_event(ctx, MFC_PU_INT_MAILBOX_AVAILABLE_EVENT);
132 		ctx->csa.priv1.int_mask_class2_RW |= CLASS2_ENABLE_MAILBOX_INTR;
135 	spin_unlock(&ctx->csa.register_lock);
139 static int spu_backing_wbox_write(struct spu_context *ctx, u32 data)
143 	spin_lock(&ctx->csa.register_lock);
144 	if ((ctx->csa.prob.mb_stat_R) & 0x00ff00) {
145 		int slot = ctx->csa.spu_chnlcnt_RW[29];
146 		int avail = (ctx->csa.prob.mb_stat_R & 0x00ff00) >> 8;
153 		ctx->csa.spu_mailbox_data[slot] = data;
154 		ctx->csa.spu_chnlcnt_RW[29] = ++slot;
155 		ctx->csa.prob.mb_stat_R &= ~(0x00ff00);
156 		ctx->csa.prob.mb_stat_R |= (((4 - slot) & 0xff) << 8);
157 		gen_spu_event(ctx, MFC_SPU_MAILBOX_WRITTEN_EVENT);
162 		ctx->csa.priv1.int_mask_class2_RW |=
166 	spin_unlock(&ctx->csa.register_lock);
170 static u32 spu_backing_signal1_read(struct spu_context *ctx)
172 	return ctx->csa.spu_chnldata_RW[3];
175 static void spu_backing_signal1_write(struct spu_context *ctx, u32 data)
177 	spin_lock(&ctx->csa.register_lock);
178 	if (ctx->csa.priv2.spu_cfg_RW & 0x1)
179 		ctx->csa.spu_chnldata_RW[3] |= data;
181 		ctx->csa.spu_chnldata_RW[3] = data;
182 	ctx->csa.spu_chnlcnt_RW[3] = 1;
183 	gen_spu_event(ctx, MFC_SIGNAL_1_EVENT);
184 	spin_unlock(&ctx->csa.register_lock);
187 static u32 spu_backing_signal2_read(struct spu_context *ctx)
189 	return ctx->csa.spu_chnldata_RW[4];
192 static void spu_backing_signal2_write(struct spu_context *ctx, u32 data)
194 	spin_lock(&ctx->csa.register_lock);
195 	if (ctx->csa.priv2.spu_cfg_RW & 0x2)
196 		ctx->csa.spu_chnldata_RW[4] |= data;
198 		ctx->csa.spu_chnldata_RW[4] = data;
199 	ctx->csa.spu_chnlcnt_RW[4] = 1;
200 	gen_spu_event(ctx, MFC_SIGNAL_2_EVENT);
201 	spin_unlock(&ctx->csa.register_lock);
204 static void spu_backing_signal1_type_set(struct spu_context *ctx, u64 val)
208 	spin_lock(&ctx->csa.register_lock);
209 	tmp = ctx->csa.priv2.spu_cfg_RW;
214 	ctx->csa.priv2.spu_cfg_RW = tmp;
215 	spin_unlock(&ctx->csa.register_lock);
218 static u64 spu_backing_signal1_type_get(struct spu_context *ctx)
220 	return ((ctx->csa.priv2.spu_cfg_RW & 1) != 0);
223 static void spu_backing_signal2_type_set(struct spu_context *ctx, u64 val)
227 	spin_lock(&ctx->csa.register_lock);
228 	tmp = ctx->csa.priv2.spu_cfg_RW;
233 	ctx->csa.priv2.spu_cfg_RW = tmp;
234 	spin_unlock(&ctx->csa.register_lock);
237 static u64 spu_backing_signal2_type_get(struct spu_context *ctx)
239 	return ((ctx->csa.priv2.spu_cfg_RW & 2) != 0);
242 static u32 spu_backing_npc_read(struct spu_context *ctx)
244 	return ctx->csa.prob.spu_npc_RW;
247 static void spu_backing_npc_write(struct spu_context *ctx, u32 val)
249 	ctx->csa.prob.spu_npc_RW = val;
252 static u32 spu_backing_status_read(struct spu_context *ctx)
254 	return ctx->csa.prob.spu_status_R;
257 static char *spu_backing_get_ls(struct spu_context *ctx)
259 	return ctx->csa.lscsa->ls;
262 static void spu_backing_privcntl_write(struct spu_context *ctx, u64 val)
264 	ctx->csa.priv2.spu_privcntl_RW = val;
267 static u32 spu_backing_runcntl_read(struct spu_context *ctx)
269 	return ctx->csa.prob.spu_runcntl_RW;
272 static void spu_backing_runcntl_write(struct spu_context *ctx, u32 val)
274 	spin_lock(&ctx->csa.register_lock);
275 	ctx->csa.prob.spu_runcntl_RW = val;
277 		ctx->csa.prob.spu_status_R &=
283 		ctx->csa.prob.spu_status_R |= SPU_STATUS_RUNNING;
285 		ctx->csa.prob.spu_status_R &= ~SPU_STATUS_RUNNING;
287 	spin_unlock(&ctx->csa.register_lock);
290 static void spu_backing_runcntl_stop(struct spu_context *ctx)
292 	spu_backing_runcntl_write(ctx, SPU_RUNCNTL_STOP);
295 static void spu_backing_master_start(struct spu_context *ctx)
297 	struct spu_state *csa = &ctx->csa;
306 static void spu_backing_master_stop(struct spu_context *ctx)
308 	struct spu_state *csa = &ctx->csa;
317 static int spu_backing_set_mfc_query(struct spu_context * ctx, u32 mask,
320 	struct spu_problem_collapsed *prob = &ctx->csa.prob;
323 	spin_lock(&ctx->csa.register_lock);
336 	ctx->csa.prob.dma_tagstatus_R &= mask;
338 	spin_unlock(&ctx->csa.register_lock);
343 static u32 spu_backing_read_mfc_tagstatus(struct spu_context * ctx)
345 	return ctx->csa.prob.dma_tagstatus_R;
348 static u32 spu_backing_get_mfc_free_elements(struct spu_context *ctx)
350 	return ctx->csa.prob.dma_qstatus_R;
353 static int spu_backing_send_mfc_command(struct spu_context *ctx,
358 	spin_lock(&ctx->csa.register_lock);
361 	spin_unlock(&ctx->csa.register_lock);
366 static void spu_backing_restart_dma(struct spu_context *ctx)
368 	ctx->csa.priv2.mfc_control_RW |= MFC_CNTL_RESTART_DMA_COMMAND;