Lines Matching defs:msr
19 u64 msr = vcpu->arch.shregs.msr;
23 if (MSR_TM_SUSPENDED(vcpu->arch.shregs.msr))
25 if (msr & MSR_PR) {
45 u64 msr = vcpu->arch.shregs.msr;
74 WARN_ON_ONCE(!(MSR_TM_SUSPENDED(msr) &&
78 vcpu->arch.shregs.msr = newmsr;
84 if ((msr & MSR_PR) && (vcpu->arch.vcore->pcr & PCR_ARCH_206)) {
96 if ((msr & MSR_PR) && !(vcpu->arch.fscr & FSCR_EBB)) {
105 WARN_ON_ONCE(!(MSR_TM_SUSPENDED(msr) &&
111 msr = (msr & ~MSR_TS_MASK) | MSR_TS_T;
112 vcpu->arch.shregs.msr = msr;
122 WARN_ON_ONCE(!(MSR_TM_SUSPENDED(msr) &&
126 newmsr = (newmsr & ~MSR_LE) | (msr & MSR_LE);
128 vcpu->arch.shregs.msr = newmsr;
135 if ((msr & MSR_PR) && (vcpu->arch.vcore->pcr & PCR_ARCH_206)) {
147 if (!(msr & MSR_TM)) {
157 (((msr & MSR_TS_MASK) >> MSR_TS_S_LG) << 29);
160 if (MSR_TM_SUSPENDED(msr))
161 msr = (msr & ~MSR_TS_MASK) | MSR_TS_T;
163 if (MSR_TM_TRANSACTIONAL(msr))
164 msr = (msr & ~MSR_TS_MASK) | MSR_TS_S;
166 vcpu->arch.shregs.msr = msr;
179 if (!(msr & MSR_TM)) {
188 if (!MSR_TM_ACTIVE(msr)) {
204 (((msr & MSR_TS_MASK) >> MSR_TS_S_LG) << 29);
205 vcpu->arch.shregs.msr &= ~MSR_TS_MASK;
219 if (!(msr & MSR_TM)) {
228 if (MSR_TM_ACTIVE(msr) || !(vcpu->arch.texasr & TEXASR_FS)) {
237 (((msr & MSR_TS_MASK) >> MSR_TS_S_LG) << 29);
238 vcpu->arch.shregs.msr = msr | MSR_TS_S;