Lines Matching refs:r9
69 lwz r9,_MSR(r11) /* if sleeping, clear MSR.EE */
70 rlwinm r9,r9,0,~MSR_EE
79 lwz r9, THREAD+THSR0(r2)
80 update_user_segments_by_4 r9, r10, r11, r12
85 lwz r9, THREAD+THSR0(r2)
86 rlwinm r9,r9,0,~SR_NX
87 update_user_segments_by_4 r9, r10, r11, r12
112 rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */
117 stw r9,_MSR(r1)
218 andi. r10,r9,MSR_RI /* check for recoverable interrupt */
234 mtspr SPRN_SRR1,r9
363 mtspr SPRN_SPRG_WSCRATCH0, r9
365 mtspr SPRN_SPRG_SCRATCH0, r9
367 addi r9,r1,INT_FRAME_SIZE /* get original r1 */
371 stw r9,0(r1) /* perform store component of stwu */
373 mfspr r9, SPRN_SPRG_RSCRATCH0
375 mfspr r9, SPRN_SPRG_SCRATCH0
427 lwz r9,_DEAR(r1); \
429 mtspr SPRN_DEAR,r9; \
441 lwz r9,_##exc_lvl_srr0(r1); \
443 mtspr SPRN_##exc_lvl_srr0,r9; \
455 lwz r9,MAS0(r1); \
458 mtspr SPRN_MAS0,r9; \
459 lwz r9,MAS3(r1); \
463 mtspr SPRN_MAS3,r9; \
468 lwz r9,MMUCR(r1); \
469 mtspr SPRN_MMUCR,r9;
477 lis r9,crit_srr0@ha;
478 lwz r9,crit_srr0@l(r9);
481 mtspr SPRN_SRR0,r9;