Lines Matching defs:bar1_index
711 union cvmx_npei_bar1_indexx bar1_index;
931 bar1_index.u32 = 0;
932 bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
933 bar1_index.s.ca = 1; /* Not Cached */
934 bar1_index.s.end_swp = 1; /* Endian Swap mode */
935 bar1_index.s.addr_v = 1; /* Valid entry */
947 bar1_index.u32);
950 bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);
1168 union cvmx_pemx_bar1_indexx bar1_index;
1414 bar1_index.u64 = 0;
1415 bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
1416 bar1_index.s.ca = 1; /* Not Cached */
1417 bar1_index.s.end_swp = 1; /* Endian Swap mode */
1418 bar1_index.s.addr_v = 1; /* Valid entry */
1421 cvmx_write_csr(CVMX_PEMX_BAR1_INDEXX(i, pcie_port), bar1_index.u64);
1423 bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);