mips/pci/pci-xtalk-bridge.c

32 	struct bridge_controller *bc = BRIDGE_CONTROLLER(pdev->bus);
34 	return bc->baddr + paddr;
97 	struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
101 	bridge_clr(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR);
102 	bridge_read(bc, b_widget.w_tflush);	/* Flush */
122 	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
123 	struct bridge_regs *bridge = bc->base;
141 				   bc->ioc3_sid[slot]);
159 	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
160 	struct bridge_regs *bridge = bc->base;
168 	bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
180 				   bc->ioc3_sid[slot]);
207 	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
208 	struct bridge_regs *bridge = bc->base;
246 	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
247 	struct bridge_regs *bridge = bc->base;
255 	bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
299 	struct bridge_controller *bc;
316 		bridge_write(data->bc, b_int_addr[pin].addr,
317 			     (((data->bc->intr_addr >> 30) & 0x30000) |
319 		bridge_read(data->bc, b_wid_tflush);
350 		data->bc = info->ctrl;
377 	struct bridge_controller *bc = data->bc;
382 	bridge_write(bc, b_int_addr[pin].addr,
383 		     (((bc->intr_addr >> 30) & 0x30000) |
385 	bridge_set(bc, b_int_enable, (1 << pin));
386 	bridge_set(bc, b_int_enable, 0x7ffffe00); /* more stuff in int_enable */
395 	bridge_set(bc, b_int_mode, (1UL << pin));
401 	device = bridge_read(bc, b_int_device);
404 	bridge_write(bc, b_int_device, device);
406 	bridge_read(bc, b_wid_tflush);
415 	bridge_clr(data->bc, b_int_enable, (1 << irqd->hwirq));
416 	bridge_read(data->bc, b_wid_tflush);
437 	struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
452 	irq = bc->pci_int[slot][pin];
454 		info.ctrl = bc;
455 		info.nasid = bc->nasid;
456 		info.pin = bc->int_mapping[slot][pin];
458 		irq = irq_domain_alloc_irqs(bc->domain, 1, bc->nasid, &info);
462 		bc->pci_int[slot][pin] = irq;
469 static void bridge_setup_ip27_baseio6g(struct bridge_controller *bc)
471 	bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP27_BASEIO6G);
472 	bc->ioc3_sid[6] = IOC3_SID(IOC3_SUBSYS_IP27_MIO);
473 	bc->int_mapping[2][1] = 4;
474 	bc->int_mapping[6][1] = 6;
477 static void bridge_setup_ip27_baseio(struct bridge_controller *bc)
479 	bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP27_BASEIO);
480 	bc->int_mapping[2][1] = 4;
483 static void bridge_setup_ip29_baseio(struct bridge_controller *bc)
485 	bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP29_SYSBOARD);
486 	bc->int_mapping[2][1] = 3;
489 static void bridge_setup_ip30_sysboard(struct bridge_controller *bc)
491 	bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP30_SYSBOARD);
492 	bc->int_mapping[2][1] = 4;
495 static void bridge_setup_menet(struct bridge_controller *bc)
497 	bc->ioc3_sid[0] = IOC3_SID(IOC3_SUBSYS_MENET);
498 	bc->ioc3_sid[1] = IOC3_SID(IOC3_SUBSYS_MENET);
499 	bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_MENET);
500 	bc->ioc3_sid[3] = IOC3_SID(IOC3_SUBSYS_MENET4);
503 static void bridge_setup_io7(struct bridge_controller *bc)
505 	bc->ioc3_sid[4] = IOC3_SID(IOC3_SUBSYS_IO7);
508 static void bridge_setup_io8(struct bridge_controller *bc)
510 	bc->ioc3_sid[4] = IOC3_SID(IOC3_SUBSYS_IO8);
513 static void bridge_setup_io9(struct bridge_controller *bc)
515 	bc->ioc3_sid[1] = IOC3_SID(IOC3_SUBSYS_IO9);
518 static void bridge_setup_ip34_fuel_sysboard(struct bridge_controller *bc)
520 	bc->ioc3_sid[4] = IOC3_SID(IOC3_SUBSYS_IP34_SYSBOARD);
528 	void (*setup)(struct bridge_controller *bc);
546 static void bridge_setup_board(struct bridge_controller *bc, char *partnum)
553 			bridge_ioc3_devid[i].setup(bc);
611 	struct bridge_controller *bc;
638 	host = devm_pci_alloc_host_bridge(dev, sizeof(*bc));
644 	bc = pci_host_bridge_priv(host);
646 	bc->busn.name		= "Bridge PCI busn";
647 	bc->busn.start		= 0;
648 	bc->busn.end		= 0xff;
649 	bc->busn.flags		= IORESOURCE_BUS;
651 	bc->domain		= domain;
655 	pci_add_resource(&host->windows, &bc->busn);
661 	bc->nasid = bd->nasid;
663 	bc->baddr = (u64)bd->masterwid << 60 | PCI64_ATTR_BAR;
664 	bc->base = (struct bridge_regs *)bd->bridge_addr;
665 	bc->intr_addr = bd->intr_addr;
670 	bridge_write(bc, b_int_rst_stat, BRIDGE_IRR_ALL_CLR);
675 	bridge_write(bc, b_int_device, 0x0);
680 	bridge_clr(bc, b_wid_control,
683 	bridge_clr(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
685 	bridge_set(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
692 	bridge_write(bc, b_wid_int_upper,
693 		     ((bc->intr_addr >> 32) & 0xffff) | (bd->masterwid << 16));
694 	bridge_write(bc, b_wid_int_lower, bc->intr_addr & 0xffffffff);
695 	bridge_write(bc, b_dir_map, (bd->masterwid << 20));	/* DMA */
696 	bridge_write(bc, b_int_enable, 0);
699 		bridge_set(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR);
700 		bc->pci_int[slot][0] = -1;
701 		bc->pci_int[slot][1] = -1;
703 		bc->int_mapping[slot][0] = slot;
704 		bc->int_mapping[slot][1] = slot ^ 4;
706 	bridge_read(bc, b_wid_tflush);	  /* wait until Bridge PIO complete */
708 	bridge_setup_board(bc, partnum);
711 	host->sysdata = bc;
739 	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
740 	struct fwnode_handle *fn = bc->domain->fwnode;
742 	irq_domain_remove(bc->domain);