Lines Matching refs:ctl_status_2
362 union cvmx_pci_ctl_status_2 ctl_status_2;
386 ctl_status_2.u32 = 0;
387 ctl_status_2.s.tsr_hwm = 1; /* Initializes to 0. Must be set
389 ctl_status_2.s.bar2pres = 1; /* Enable BAR2 */
390 ctl_status_2.s.bar2_enb = 1;
391 ctl_status_2.s.bar2_cax = 1; /* Don't use L2 */
392 ctl_status_2.s.bar2_esx = 1;
393 ctl_status_2.s.pmo_amod = 1; /* Round robin priority */
396 ctl_status_2.s.bb1_hole = OCTEON_PCI_BAR1_HOLE_BITS;
397 ctl_status_2.s.bb1_siz = 1; /* BAR1 is 2GB */
398 ctl_status_2.s.bb_ca = 1; /* Don't use L2 with big bars */
399 ctl_status_2.s.bb_es = 1; /* Big bar in byte swap mode */
400 ctl_status_2.s.bb1 = 1; /* BAR1 is big */
401 ctl_status_2.s.bb0 = 1; /* BAR0 is big */
404 octeon_npi_write32(CVMX_NPI_PCI_CTL_STATUS_2, ctl_status_2.u32);
407 ctl_status_2.u32 = octeon_npi_read32(CVMX_NPI_PCI_CTL_STATUS_2);
409 ctl_status_2.s.ap_pcix ? "PCI-X" : "PCI",
410 ctl_status_2.s.ap_64ad ? "64" : "32");
435 if (ctl_status_2.s.ap_pcix) {