mips/pci/pci-malta.c

30 	.start	= 0x00000000UL,
81 	resource_size_t start, end, map, start1, end1, map1, map2, map3, mask;
103 		start = GT_READ(GT_PCI0M0LD_OFS);
106 		end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);
112 		if (end1 - start1 > end - start) {
113 			start = start1;
117 		mask = ~(start ^ end);
119 		BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
121 		gt64120_mem_resource.start = start;
123 		gt64120_controller.mem_offset = (start & mask) - (map & mask);
125 		gt64120_mem_resource.start <<= GT_PCI_DCRM_SHF;
130 		start = GT_READ(GT_PCI0IOLD_OFS);
133 		end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);
134 		mask = ~(start ^ end);
136 		BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
138 		gt64120_io_resource.start = map & mask;
142 		gt64120_io_resource.start <<= GT_PCI_DCRM_SHF;
160 		start = BONITO_PCILO0_BASE;
164 			start = BONITO_PCILO1_BASE;
169 			start = BONITO_PCILO0_BASE;
172 		bonito64_mem_resource.start = start;
173 		bonito64_mem_resource.end = start +
175 		bonito64_controller.mem_offset = start -
186 		MSC_READ(MSC01_PCI_SC2PMBASL, start);
189 		msc_mem_resource.start = start & mask;
190 		msc_mem_resource.end = (start & mask) | ~mask;
191 		msc_controller.mem_offset = (start & mask) - (map & mask);
193 			write_gcr_reg0_base(start);
197 		MSC_READ(MSC01_PCI_SC2PIOBASL, start);
200 		msc_io_resource.start = map & mask;
205 			write_gcr_reg1_base(start);
210 		start = start & mask;
211 		end = start | ~mask;
212 		if ((start >= msc_mem_resource.start &&
213 		     start <= msc_mem_resource.end) ||
214 		    (end >= msc_mem_resource.start &&
217 			start = max(start, msc_mem_resource.start);
219 			if (start - msc_mem_resource.start >=
221 				msc_mem_resource.end = start - 1;
223 				msc_mem_resource.start = end + 1;
233 	if (controller->io_resource->start < 0x00001000UL)
234 		controller->io_resource->start = 0x00001000UL;