Lines Matching defs:bit
59 /* convert condition code register number to csr bit */
78 * This functions translates a 32-bit microMIPS instruction
79 * into a 32-bit MIPS32 instruction. Returns 0 on success
429 unsigned int bit = 0;
504 set_isa16_mode(bit);
516 /* Set microMIPS mode bit: XOR for jalx. */
517 *contpc ^= bit;
705 bit = 0;
710 bit = bit0 == 0;
713 bit = bit0 != 0;
716 if (bit)
739 bit = (insn.i_format.rt >> 2);
740 bit += (bit != 0);
741 bit += 23;
745 if (~fcr31 & (1 << bit))
756 if (fcr31 & (1 << bit))
774 * basis of the Status.FR bit. If an FPU is not present, the FR bit
775 * is hardwired to zero, which would imply a 32-bit FPU even for
776 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
779 * a constant whenever possible, that is on 64-bit kernels without O32
780 * compatibility enabled and on 32-bit without 64-bit FPU support.
1030 * are not a subset. Example: Cannot emulate a 16-bit
1035 * If next instruction is a 16-bit instruction, then
1253 /* If 16-bit instruction, not FPU. */
1260 * 32-bit words, get around
2860 * into 32-bit instructions.
2876 /* 16-bit instruction. */
2882 /* 32-bit instruction. */
2891 /* 16-bit instruction. */
2896 /* 32-bit instruction. */
2930 * We have to check for the ISA bit explicitly here,