mips/kvm/vz.c

425 	struct mips_coproc *cop0 = &vcpu->arch.cop0;
428 	compare = kvm_read_sw_gc0_compare(cop0);
429 	cause = kvm_read_sw_gc0_cause(cop0);
520 	struct mips_coproc *cop0 = &vcpu->arch.cop0;
536 	kvm_write_sw_gc0_cause(cop0, cause);
537 	kvm_write_sw_gc0_compare(cop0, compare);
866 	struct mips_coproc *cop0 = &vcpu->arch.cop0;
870 		kvm_write_sw_gc0_maari(cop0, ARRAY_SIZE(vcpu->arch.maar) - 1);
872 		kvm_write_sw_gc0_maari(cop0, val);
879 	struct mips_coproc *cop0 = &vcpu->arch.cop0;
911 			cop0->stat[rd][sel]++;
931 				BUG_ON(kvm_read_sw_gc0_maari(cop0) >=
934 					kvm_read_sw_gc0_maari(cop0)];
951 				val = cop0->reg[rd][sel];
955 				val = cop0->reg[rd][sel];
977 			cop0->stat[rd][sel]++;
1010 				BUG_ON(kvm_read_sw_gc0_maari(cop0) >=
1012 				vcpu->arch.maar[kvm_read_sw_gc0_maari(cop0)] =
1021 				cop0->reg[rd][sel] = (int)val;
1065 		kvm_err("[%#lx]%s: unsupported cop0 instruction 0x%08x\n",
1914 	struct mips_coproc *cop0 = &vcpu->arch.cop0;
2035 			*v = (long)kvm_read_c0_guest_prid(cop0);
2071 		*v = kvm_read_sw_gc0_config6(cop0);
2084 		*v = kvm_read_sw_gc0_maari(&vcpu->arch.cop0);
2138 	struct mips_coproc *cop0 = &vcpu->arch.cop0;
2277 			kvm_write_c0_guest_prid(cop0, v);
2343 		cur = kvm_read_sw_gc0_config6(cop0);
2347 			kvm_write_sw_gc0_config6(cop0, (int)v);
2565 	struct mips_coproc *cop0 = &vcpu->arch.cop0;
2585 	kvm_restore_gc0_wired(cop0);
2613 	kvm_restore_gc0_config(cop0);
2615 		kvm_restore_gc0_config1(cop0);
2617 		kvm_restore_gc0_config2(cop0);
2619 		kvm_restore_gc0_config3(cop0);
2621 		kvm_restore_gc0_config4(cop0);
2623 		kvm_restore_gc0_config5(cop0);
2625 		kvm_restore_gc0_config6(cop0);
2627 		kvm_restore_gc0_config7(cop0);
2629 	kvm_restore_gc0_index(cop0);
2630 	kvm_restore_gc0_entrylo0(cop0);
2631 	kvm_restore_gc0_entrylo1(cop0);
2632 	kvm_restore_gc0_context(cop0);
2634 		kvm_restore_gc0_contextconfig(cop0);
2636 	kvm_restore_gc0_xcontext(cop0);
2638 		kvm_restore_gc0_xcontextconfig(cop0);
2640 	kvm_restore_gc0_pagemask(cop0);
2641 	kvm_restore_gc0_pagegrain(cop0);
2642 	kvm_restore_gc0_hwrena(cop0);
2643 	kvm_restore_gc0_badvaddr(cop0);
2644 	kvm_restore_gc0_entryhi(cop0);
2645 	kvm_restore_gc0_status(cop0);
2646 	kvm_restore_gc0_intctl(cop0);
2647 	kvm_restore_gc0_epc(cop0);
2648 	kvm_vz_write_gc0_ebase(kvm_read_sw_gc0_ebase(cop0));
2650 		kvm_restore_gc0_userlocal(cop0);
2652 	kvm_restore_gc0_errorepc(cop0);
2657 			kvm_restore_gc0_kscratch1(cop0);
2659 			kvm_restore_gc0_kscratch2(cop0);
2661 			kvm_restore_gc0_kscratch3(cop0);
2663 			kvm_restore_gc0_kscratch4(cop0);
2665 			kvm_restore_gc0_kscratch5(cop0);
2667 			kvm_restore_gc0_kscratch6(cop0);
2671 		kvm_restore_gc0_badinstr(cop0);
2673 		kvm_restore_gc0_badinstrp(cop0);
2676 		kvm_restore_gc0_segctl0(cop0);
2677 		kvm_restore_gc0_segctl1(cop0);
2678 		kvm_restore_gc0_segctl2(cop0);
2683 		kvm_restore_gc0_pwbase(cop0);
2684 		kvm_restore_gc0_pwfield(cop0);
2685 		kvm_restore_gc0_pwsize(cop0);
2686 		kvm_restore_gc0_pwctl(cop0);
2692 			cop0->reg[MIPS_CP0_GUESTCTL2][MIPS_CP0_GUESTCTL2_SEL]);
2707 	struct mips_coproc *cop0 = &vcpu->arch.cop0;
2714 	kvm_save_gc0_index(cop0);
2715 	kvm_save_gc0_entrylo0(cop0);
2716 	kvm_save_gc0_entrylo1(cop0);
2717 	kvm_save_gc0_context(cop0);
2719 		kvm_save_gc0_contextconfig(cop0);
2721 	kvm_save_gc0_xcontext(cop0);
2723 		kvm_save_gc0_xcontextconfig(cop0);
2725 	kvm_save_gc0_pagemask(cop0);
2726 	kvm_save_gc0_pagegrain(cop0);
2727 	kvm_save_gc0_wired(cop0);
2730 	kvm_save_gc0_hwrena(cop0);
2731 	kvm_save_gc0_badvaddr(cop0);
2732 	kvm_save_gc0_entryhi(cop0);
2733 	kvm_save_gc0_status(cop0);
2734 	kvm_save_gc0_intctl(cop0);
2735 	kvm_save_gc0_epc(cop0);
2736 	kvm_write_sw_gc0_ebase(cop0, kvm_vz_read_gc0_ebase());
2738 		kvm_save_gc0_userlocal(cop0);
2741 	kvm_save_gc0_config(cop0);
2743 		kvm_save_gc0_config1(cop0);
2745 		kvm_save_gc0_config2(cop0);
2747 		kvm_save_gc0_config3(cop0);
2749 		kvm_save_gc0_config4(cop0);
2751 		kvm_save_gc0_config5(cop0);
2753 		kvm_save_gc0_config6(cop0);
2755 		kvm_save_gc0_config7(cop0);
2757 	kvm_save_gc0_errorepc(cop0);
2762 			kvm_save_gc0_kscratch1(cop0);
2764 			kvm_save_gc0_kscratch2(cop0);
2766 			kvm_save_gc0_kscratch3(cop0);
2768 			kvm_save_gc0_kscratch4(cop0);
2770 			kvm_save_gc0_kscratch5(cop0);
2772 			kvm_save_gc0_kscratch6(cop0);
2776 		kvm_save_gc0_badinstr(cop0);
2778 		kvm_save_gc0_badinstrp(cop0);
2781 		kvm_save_gc0_segctl0(cop0);
2782 		kvm_save_gc0_segctl1(cop0);
2783 		kvm_save_gc0_segctl2(cop0);
2788 	    kvm_read_sw_gc0_config3(cop0) & MIPS_CONF3_PW)) {
2789 		kvm_save_gc0_pwbase(cop0);
2790 		kvm_save_gc0_pwfield(cop0);
2791 		kvm_save_gc0_pwsize(cop0);
2792 		kvm_save_gc0_pwctl(cop0);
2799 		cop0->reg[MIPS_CP0_GUESTCTL2][MIPS_CP0_GUESTCTL2_SEL] =
3079 	struct mips_coproc *cop0 = &vcpu->arch.cop0;
3096 		kvm_write_sw_gc0_pagegrain(cop0, PG_RIE | PG_XIE | PG_IEC);
3099 		kvm_write_sw_gc0_wired(cop0,
3102 	kvm_write_sw_gc0_status(cop0, ST0_BEV | ST0_ERL);
3104 		kvm_change_sw_gc0_status(cop0, ST0_FR, read_gc0_status());
3106 	kvm_write_sw_gc0_intctl(cop0, read_gc0_intctl() &
3109 	kvm_write_sw_gc0_prid(cop0, boot_cpu_data.processor_id);
3111 	kvm_write_sw_gc0_ebase(cop0, (s32)0x80000000 | vcpu->vcpu_id);
3113 	kvm_save_gc0_config(cop0);
3115 	kvm_change_sw_gc0_config(cop0, CONF_CM_CMASK,
3118 	kvm_change_sw_gc0_config(cop0, MIPS_CONF_MT, read_c0_config());
3120 		kvm_set_sw_gc0_config(cop0, MIPS_CONF_M);
3122 		kvm_save_gc0_config1(cop0);
3124 		kvm_clear_sw_gc0_config1(cop0, MIPS_CONF1_C2	|
3132 		kvm_set_sw_gc0_config1(cop0, MIPS_CONF_M);
3134 		kvm_save_gc0_config2(cop0);
3137 		kvm_set_sw_gc0_config2(cop0, MIPS_CONF_M);
3139 		kvm_save_gc0_config3(cop0);
3141 		kvm_clear_sw_gc0_config3(cop0, MIPS_CONF3_ISA_OE);
3143 		kvm_clear_sw_gc0_config3(cop0, MIPS_CONF3_MSA	|
3159 		kvm_set_sw_gc0_config3(cop0, MIPS_CONF_M);
3161 		kvm_save_gc0_config4(cop0);
3164 		kvm_set_sw_gc0_config4(cop0, MIPS_CONF_M);
3166 		kvm_save_gc0_config5(cop0);
3168 		kvm_clear_sw_gc0_config5(cop0, MIPS_CONF5_K	|
3176 		kvm_clear_sw_gc0_config5(cop0, MIPS_CONF5_MRP);
3181 		kvm_write_sw_gc0_contextconfig(cop0, 0x007ffff0);
3185 		kvm_write_sw_gc0_xcontextconfig(cop0,
3193 		kvm_write_sw_gc0_segctl0(cop0, 0x00200010);
3194 		kvm_write_sw_gc0_segctl1(cop0, 0x00000002 |
3197 		kvm_write_sw_gc0_segctl2(cop0, 0x00380438);
3203 		kvm_write_sw_gc0_pwfield(cop0, 0x0c30c302);
3205 		kvm_write_sw_gc0_pwsize(cop0, 1 << MIPS_PWSIZE_PTW_SHIFT);
3210 		cop0->reg[MIPS_CP0_GUESTCTL2][MIPS_CP0_GUESTCTL2_SEL] = 0;