mips/kvm/vz.c

881 	u32 rt, rd, sel;
904 		rd = inst.c0r_format.rd;
911 			cop0->stat[rd][sel]++;
913 			if (rd == MIPS_CP0_COUNT &&
916 			} else if (rd == MIPS_CP0_COMPARE &&
919 			} else if (rd == MIPS_CP0_LLADDR &&
926 			} else if (rd == MIPS_CP0_LLADDR &&
935 			} else if ((rd == MIPS_CP0_PRID &&
939 				   (rd == MIPS_CP0_STATUS &&
942 				   (rd == MIPS_CP0_CONFIG &&
945 				   (rd == MIPS_CP0_LLADDR &&
949 				   (rd == MIPS_CP0_ERRCTL &&
951 				val = cop0->reg[rd][sel];
953 			} else if (rd == MIPS_CP0_DIAG &&
955 				val = cop0->reg[rd][sel];
971 				      KVM_TRACE_COP0(rd, sel), val);
977 			cop0->stat[rd][sel]++;
982 				      KVM_TRACE_COP0(rd, sel), val);
984 			if (rd == MIPS_CP0_COUNT &&
988 			} else if (rd == MIPS_CP0_COMPARE &&
993 			} else if (rd == MIPS_CP0_LLADDR &&
1002 			} else if (rd == MIPS_CP0_LLADDR &&
1014 			} else if (rd == MIPS_CP0_LLADDR &&
1019 			} else if (rd == MIPS_CP0_CONFIG &&
1021 				cop0->reg[rd][sel] = (int)val;
1022 			} else if (rd == MIPS_CP0_ERRCTL &&
1026 			} else if (rd == MIPS_CP0_DIAG &&
1147 	unsigned int rs, rd;
1162 	rd = inst.loongson3_lscsr_format.rd;
1170 			vcpu->arch.gprs[rd] = 0x14c000;
1176 			vcpu->arch.gprs[rd] = hostcfg;
1181 			vcpu->arch.gprs[rd] = hostcfg;
1184 			vcpu->arch.gprs[rd] = hostcfg;
1188 			vcpu->arch.gprs[rd] = 0;
1218 	int rd, rt, sel;
1257 			rd = inst.r_format.rd;
1261 			switch (rd) {
1268 					      KVM_TRACE_HWR(rd, sel), 0);
1273 				      KVM_TRACE_HWR(rd, sel), arch->gprs[rt]);
1316 		int rd = inst.c0r_format.rd;
1321 		trace_kvm_hwr(vcpu, KVM_TRACE_MTC0, KVM_TRACE_COP0(rd, sel),
1324 		if ((rd == MIPS_CP0_STATUS) && (sel == 0)) {
1360 		} else if ((rd == MIPS_CP0_CAUSE) && (sel == 0)) {
1382 		} else if ((rd == MIPS_CP0_STATUS) && (sel == 1)) { /* IntCtl */
1384 		} else if ((rd == MIPS_CP0_CONFIG) && (sel == 5)) {