mips/kernel/unaligned.c

116 	union mips_instruction insn;
128 	__get_inst32(&insn.word, pc, user);
130 	switch (insn.i_format.opcode) {
166 		if (insn.mxu_lx_format.func != mxu_lx_op)
169 		switch (insn.mxu_lx_format.op) {
177 			regs->regs[insn.mxu_lx_format.rd] = value;
186 			regs->regs[insn.dsp_format.rd] = value;
195 			regs->regs[insn.dsp_format.rd] = value;
206 		if (insn.dsp_format.func == lx_op) {
207 			switch (insn.dsp_format.op) {
215 				regs->regs[insn.dsp_format.rd] = value;
224 				regs->regs[insn.dsp_format.rd] = value;
237 			switch (insn.spec3_format.func) {
245 				regs->regs[insn.spec3_format.rt] = value;
254 				regs->regs[insn.spec3_format.rt] = value;
263 				regs->regs[insn.spec3_format.rt] = value;
269 				value = regs->regs[insn.spec3_format.rt];
278 				value = regs->regs[insn.spec3_format.rt];
301 		regs->regs[insn.i_format.rt] = value;
316 		regs->regs[insn.i_format.rt] = value;
331 		regs->regs[insn.i_format.rt] = value;
350 		regs->regs[insn.i_format.rt] = value;
373 		regs->regs[insn.i_format.rt] = value;
385 		value = regs->regs[insn.i_format.rt];
401 		value = regs->regs[insn.i_format.rt];
425 		value = regs->regs[insn.i_format.rt];
477 		df = insn.msa_mi10_format.df;
478 		wd = insn.msa_mi10_format.wd;
481 		switch (insn.msa_mi10_format.func) {
627 	union mips_instruction insn;
653 	mminsn.insn = word;
669 	insn = (union mips_instruction)(mminsn.insn);
671 		insn = (union mips_instruction)(mminsn.next_insn);
675 	switch (insn.mm_i_format.opcode) {
678 		switch (insn.mm_x_format.func) {
680 			reg = insn.mm_x_format.rd;
687 		switch (insn.mm_m_format.func) {
689 			reg = insn.mm_m_format.rd;
708 			reg = insn.mm_m_format.rd;
728 			reg = insn.mm_m_format.rd;
751 			reg = insn.mm_m_format.rd;
773 			reg = insn.mm_m_format.rd;
809 			reg = insn.mm_m_format.rd;
846 			reg = insn.mm_m_format.rd;
887 			reg = insn.mm_m_format.rd;
932 		switch (insn.mm_m_format.func) {
934 			reg = insn.mm_m_format.rd;
943 		switch (insn.mm_x_format.func) {
982 		reg = insn.mm_i_format.rt;
986 		reg = insn.mm_i_format.rt;
990 		reg = insn.mm_i_format.rt;
994 		reg = insn.mm_i_format.rt;
998 		reg = insn.mm_i_format.rt;
1002 		reg = insn.mm_i_format.rt;
1006 		reg = insn.mm_i_format.rt;
1010 		switch (insn.mm16_m_format.func) {
1012 			reg = insn.mm16_m_format.rlist;
1032 			reg = insn.mm16_m_format.rlist;
1056 		reg = reg16to32[insn.mm16_rb_format.rt];
1060 		reg = reg16to32[insn.mm16_rb_format.rt];
1064 		reg = reg16to32st[insn.mm16_rb_format.rt];
1068 		reg = reg16to32st[insn.mm16_rb_format.rt];
1072 		reg = insn.mm16_r5_format.rt;
1076 		reg = insn.mm16_r5_format.rt;
1080 		reg = reg16to32[insn.mm16_r3_format.rt];