Lines Matching refs:MSCIC_WRITE
21 #define MSCIC_WRITE(reg, data) do { *(volatile u32 *)(reg) = data; } while (0)
32 MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base));
34 MSCIC_WRITE(MSC01_IC_DISH, 1<<(irq - irq_base - 32));
43 MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base));
45 MSCIC_WRITE(MSC01_IC_ENAH, 1<<(irq - irq_base - 32));
55 MSCIC_WRITE(MSC01_IC_EOI, 0);
67 MSCIC_WRITE(MSC01_IC_EOI, 0);
71 MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT);
72 MSCIC_WRITE(MSC01_IC_SUP+irq*8, r);
94 MSCIC_WRITE(MSC01_IC_RAMW,
122 MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT);
136 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
138 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
146 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
148 MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl);
154 MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */