Lines Matching refs:name

30 #define GIC_ACCESSOR_RO(sz, off, name)					\
31 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_SHARED_OFS + off, name)
34 #define GIC_ACCESSOR_RW(sz, off, name) \
35 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_SHARED_OFS + off, name)
38 #define GIC_VX_ACCESSOR_RO(sz, off, name) \
39 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name) \
40 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name)
43 #define GIC_VX_ACCESSOR_RW(sz, off, name) \
44 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name) \
45 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name)
48 #define GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \
49 static inline void __iomem *addr_gic_##name(unsigned int intr) \
54 static inline unsigned int read_gic_##name(unsigned int intr) \
57 return __raw_readl(addr_gic_##name(intr)); \
61 #define GIC_ACCESSOR_RW_INTR_REG(sz, off, stride, name) \
62 GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \
64 static inline void write_gic_##name(unsigned int intr, \
68 __raw_writel(val, addr_gic_##name(intr)); \
72 #define GIC_VX_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \
74 stride, vl_##name) \
76 stride, vo_##name)
79 #define GIC_VX_ACCESSOR_RW_INTR_REG(sz, off, stride, name) \
81 stride, vl_##name) \
83 stride, vo_##name)
86 #define GIC_ACCESSOR_RO_INTR_BIT(off, name) \
87 static inline void __iomem *addr_gic_##name(void) \
92 static inline unsigned int read_gic_##name(unsigned int intr) \
94 void __iomem *addr = addr_gic_##name(); \
109 #define GIC_ACCESSOR_RW_INTR_BIT(off, name) \
110 GIC_ACCESSOR_RO_INTR_BIT(off, name) \
112 static inline void write_gic_##name(unsigned int intr) \
114 void __iomem *addr = addr_gic_##name(); \
125 static inline void change_gic_##name(unsigned int intr, \
128 void __iomem *addr = addr_gic_##name(); \
150 #define GIC_VX_ACCESSOR_RO_INTR_BIT(sz, off, name) \
152 vl_##name) \
154 vo_##name)
157 #define GIC_VX_ACCESSOR_RW_INTR_BIT(sz, off, name) \
159 vl_##name) \
161 vo_##name)