mips/cavium-octeon/octeon-irq.c

78 			u8 bit;
90 	u8 bit;
97 static int octeon_irq_set_ciu_mapping(int irq, int line, int bit, int gpio_line,
110 	cd->bit = bit;
114 	octeon_irq_ciu_to_irq[line][bit] = irq;
128 					int irq, int line, int bit)
140 	return irq_domain_associate(domain, irq, line << 6 | bit);
164 	unsigned int bit = cd->bit;
171 	clear_c0_status(0x100 << bit);
173 	if (bit < 2)
174 		clear_c0_cause(0x100 << bit);
186 	set_c0_status(0x100 << cd->bit);
193 	unsigned int mask = 0x100 << cd->bit;
261 		cd->bit = i;
317 		__set_bit(cd->bit, pen);
326 		__set_bit(cd->bit, pen);
349 		__set_bit(cd->bit, pen);
358 		__set_bit(cd->bit, pen);
381 		__clear_bit(cd->bit, pen);
390 		__clear_bit(cd->bit, pen);
420 		__clear_bit(cd->bit, pen);
453 		__set_bit(cd->bit, pen);
478 	mask = 1ull << (cd->bit);
486 		set_bit(cd->bit, &per_cpu(octeon_irq_ciu0_en_mirror, cpu));
490 		set_bit(cd->bit, &per_cpu(octeon_irq_ciu1_en_mirror, cpu));
506 	mask = 1ull << (cd->bit);
522 	mask = 1ull << (cd->bit);
535 	mask = 1ull << (cd->bit);
547 	mask = 1ull << (cd->bit);
566 	mask = 1ull << (cd->bit);
570 		set_bit(cd->bit, this_cpu_ptr(&octeon_irq_ciu0_en_mirror));
574 		set_bit(cd->bit, this_cpu_ptr(&octeon_irq_ciu1_en_mirror));
585 	mask = 1ull << (cd->bit);
589 		clear_bit(cd->bit, this_cpu_ptr(&octeon_irq_ciu0_en_mirror));
593 		clear_bit(cd->bit, this_cpu_ptr(&octeon_irq_ciu1_en_mirror));
599  * Write to the W1C bit in CVMX_CIU_INTX_SUM0 to clear the irq.
607 	mask = 1ull << (cd->bit);
628 	mask = 1ull << (cd->bit);
633 			clear_bit(cd->bit,
640 			clear_bit(cd->bit,
658 	mask = 1ull << (cd->bit);
663 			set_bit(cd->bit,
670 			set_bit(cd->bit,
828 			__set_bit(cd->bit, pen);
830 			__clear_bit(cd->bit, pen);
865 	mask = 1ull << cd->bit;
873 				set_bit(cd->bit, pen);
876 				clear_bit(cd->bit, pen);
886 				set_bit(cd->bit, pen);
889 				clear_bit(cd->bit, pen);
910 	mask = 1ull << cd->bit;
1126 static bool octeon_irq_ciu_is_edge(unsigned int line, unsigned int bit)
1131 		switch (bit) {
1142 		switch (bit) {
1212 	unsigned int ciu, bit;
1216 	bit = intspec[1];
1218 	if (ciu >= dd->num_sum || bit > 63)
1221 	*out_hwirq = (ciu << 6) | bit;
1236 	unsigned int bit = hw & 63;
1239 	if (line >= dd->num_sum || octeon_irq_ciu_to_irq[line][bit] != 0)
1243 		if (octeon_irq_ciu_is_edge(line, bit))
1244 			rv = octeon_irq_set_ciu_mapping(virq, line, bit, 0,
1248 			rv = octeon_irq_set_ciu_mapping(virq, line, bit, 0,
1252 		if (octeon_irq_ciu_is_edge(line, bit))
1253 			rv = octeon_irq_set_ciu_mapping(virq, line, bit, 0,
1257 			rv = octeon_irq_set_ciu_mapping(virq, line, bit, 0,
1268 	unsigned int line, bit;
1272 	bit = (hw + gpiod->base_hwirq) & 63;
1274 		octeon_irq_ciu_to_irq[line][bit] != 0)
1282 	r = octeon_irq_set_ciu_mapping(virq, line, bit, hw,
1306 		int bit = fls64(ciu_sum) - 1;
1307 		int irq = octeon_irq_ciu_to_irq[0][bit];
1323 		int bit = fls64(ciu_sum) - 1;
1324 		int irq = octeon_irq_ciu_to_irq[1][bit];
1342 		int bit = fls64(ciu_sum) - 1;
1343 		int irq = octeon_irq_ciu_to_irq[2][bit];
1667 	mask = 1ull << (cd->bit);
1684 	mask = 1ull << (cd->bit);
1699 	mask = 1ull << (cd->bit);
1715 	mask = 1ull << (cd->bit);
1731 	mask = 1ull << (cd->bit);
1745 	mask = 1ull << (cd->bit);
1817 	mask = 1ull << cd->bit;
1922 	unsigned int ciu, bit;
1925 	bit = intspec[1];
1927 	*out_hwirq = (ciu << 6) | bit;
1933 static bool octeon_irq_ciu2_is_edge(unsigned int line, unsigned int bit)
1938 		switch (bit) {
1948 		switch (bit) {
1963 	unsigned int bit = hw & 63;
1972 	if (line > 7 || octeon_irq_ciu_to_irq[line][bit] != 0)
1975 	if (octeon_irq_ciu2_is_edge(line, bit))
1976 		octeon_irq_set_ciu_mapping(virq, line, bit, 0,
1980 		octeon_irq_set_ciu_mapping(virq, line, bit, 0,
1996 	int bit;
2013 	bit = fls64(src) - 1;
2014 	irq = octeon_irq_ciu_to_irq[line][bit];
2139 	int bit;
2151 	en |= 1ull << cd->bit;
2165 	en &= ~(1ull << cd->bit);
2231 	cd->bit = hw;
2268 			pr_err("ERROR: CIB bit %d@%llx IRQ unhandled, disabling\n",
2279 			/* If edge, acknowledge the bit we will be sending. */