cavium-octeon/executive/cvmx-helper-xaui.c

45 int __cvmx_helper_xaui_enumerate(int interface)
50 	gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface));
58  * Probe a XAUI interface and determine the number of ports
59  * connected to it. The XAUI interface should still be down
62  * @interface: Interface to probe
64  * Returns Number of ports on the interface. Zero to disable.
66 int __cvmx_helper_xaui_probe(int interface)
73 	 * interface needs to be enabled before IPD otherwise per port
76 	mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
78 	cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64);
80 	__cvmx_helper_setup_gmx(interface, 1);
85 	 * interface to the XAUI. This allows us to use HiGig2
98 		pko_mem_port_ptrs.s.eid = interface * 4;
99 		pko_mem_port_ptrs.s.pid = interface * 16 + i;
102 	return __cvmx_helper_xaui_enumerate(interface);
106  * Bringup and enable a XAUI interface. After this call packet
110  * @interface: Interface to bring up
114 int __cvmx_helper_xaui_enable(int interface)
126 		gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
127 		gmx_cfg.s.pknd = cvmx_helper_get_ipd_port(interface, 0);
128 		cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
134 	xauiMiscCtl.u64 = cvmx_read_csr(CVMX_PCSXX_MISC_CTL_REG(interface));
136 	cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
139 	gmx_rx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(0, interface));
140 	cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0);
141 	gmx_tx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_TX_INT_EN(interface));
142 	cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0);
143 	pcsx_int_en_reg.u64 = cvmx_read_csr(CVMX_PCSXX_INT_EN_REG(interface));
144 	cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0);
149 	gmxXauiTxCtl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
153 	cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmxXauiTxCtl.u64);
156 	xauiCtl.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface));
165 	cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), xauiCtl.u64);
169 	    (CVMX_PCSXX_CONTROL1_REG(interface), union cvmx_pcsxx_control1_reg,
174 	    (CVMX_PCSXX_10GBX_STATUS_REG(interface),
179 	    (CVMX_GMXX_RX_XAUI_CTL(interface), union cvmx_gmxx_rx_xaui_ctl,
184 	gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
186 	cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
190 	    (CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg,
195 	    (CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg,
200 	gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
204 	cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), 1);
205 	cvmx_write_csr(CVMX_GMXX_TXX_SLOT(0, interface), 512);
206 	cvmx_write_csr(CVMX_GMXX_TXX_BURST(0, interface), 8192);
207 	cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
210 	cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(0, interface),
211 		       cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(0, interface)));
212 	cvmx_write_csr(CVMX_GMXX_TX_INT_REG(interface),
213 		       cvmx_read_csr(CVMX_GMXX_TX_INT_REG(interface)));
214 	cvmx_write_csr(CVMX_PCSXX_INT_REG(interface),
215 		       cvmx_read_csr(CVMX_PCSXX_INT_REG(interface)));
219 	    (CVMX_PCSXX_STATUS1_REG(interface), union cvmx_pcsxx_status1_reg,
223 	    (CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg,
227 	    (CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg,
231 	cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), gmx_rx_int_en.u64);
232 	cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64);
233 	cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), pcsx_int_en_reg.u64);
237 	cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
239 	gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
241 	cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
243 	__cvmx_interrupt_pcsx_intx_en_reg_enable(0, interface);
244 	__cvmx_interrupt_pcsx_intx_en_reg_enable(1, interface);
245 	__cvmx_interrupt_pcsx_intx_en_reg_enable(2, interface);
246 	__cvmx_interrupt_pcsx_intx_en_reg_enable(3, interface);
247 	__cvmx_interrupt_pcsxx_int_en_reg_enable(interface);
248 	__cvmx_interrupt_gmxx_enable(interface);
265 	int interface = cvmx_helper_get_interface_num(ipd_port);
271 	gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
272 	gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface));
274 	    cvmx_read_csr(CVMX_PCSXX_STATUS1_REG(interface));
285 		cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0);
286 		cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0);
287 		cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0);
305 	int interface = cvmx_helper_get_interface_num(ipd_port);
309 	gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
310 	gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface));
321 	return __cvmx_helper_xaui_enable(interface);