Lines Matching defs:and
9 THE SOFTWARE is provided on an "AS IS" basis and without warranty.
13 and any warranty against infringement with regard to the SOFTWARE
14 (INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
21 Motorola assumes no responsibility for the maintenance and support of the SOFTWARE.
23 You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE
24 so long as this entire notice is retained without alteration in any modified and/or
25 redistributed versions, and that such modified versions are clearly identified as such.
32 # and contains the entry points into the package. The user, in
40 # it makes the FPSP code easier to read and more mainatinable.
492 set nzi_mask, 0x01ffffff #clears N, Z, and I
621 # exceptional operand and plave it in the fsave state frame, and store #
631 # overflow was disabled and the trace exception was enabled, this #
665 # since, I believe, only NORMs and DENORMs can come through here,
671 # bit five of the fp extension word separates the monadic and dyadic operations
672 # that can pass through fpsp_ovfl(). remember that fcmp, ftst, and fsincos
723 # and inexact. and, the inexact is such that overflow occurred and was disabled
789 and.l &0xffff00ff,USER_FPSR(%a6) # zero all but accured field
861 # exceptional operand and plave it in the fsave state frame, and store #
867 # but the inexact exception was enabled and the result was inexact, #
871 # underflow was disabled and the trace exception was enabled, this #
909 # bit five of the fp ext word separates the monadic and dyadic operations
910 # that can pass through fpsp_unfl(). remember that fcmp, and ftst
971 # and inexact. and, the inexact is such that overflow occurred and was disabled
1063 and.l &0xffff00ff,USER_FPSR(%a6) # zero all but accured field
1143 # instructions, and (2) PACKED unimplemented data format instructions #
1145 # For UNNORM/DENORM opclass 0 and 2, the handler fetches the src #
1146 # operand from the fsave state frame and the dst operand (if dyadic) #
1149 # instruction type. Once the instruction has been emulated and result #
1153 # this exception into the FPU in the fsave state frame and then exit #
1155 # PACKED opclass 0 and 2 is similar in how the instruction is #
1156 # emulated and exceptions handled. The differences occur in how the #
1157 # handler loads the packed op (by calling get_packed() routine) and #
1160 # frame is changed to a Trace exception stack frame and an exit is #
1168 # type and jump to either _real_snan(), _real_operr(), _real_inex(), #
1175 # (1) DENORM and UNNORM (unimplemented) data types:
1190 # (2) PACKED format (unsupported) opclasses two and three:
1236 mov.l %d0,EXC_OPWORD(%a6) # store OPWORD and EXTWORD
1243 # stack frame and protocol.
1261 # precision format if the src format was single or double and the
1280 # bit five of the fp extension word separates the monadic and dyadic operations
1327 # fcmp and ftst do not store any result.
1347 and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled
1370 # An exception occurred and that exception was enabled:
1426 # If the input operand to this operation was opclass two and a single
1495 # the src operand is in FP_SRC. Call _fout() to write out the result and
1499 # Separate packed move outs from the UNNORM and DENORM move outs.
1510 and.l &0xffff00ff,USER_FPSR(%a6) # zero exception field
1616 and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled
1621 # if a disabled overflow occurred and inexact was enabled but the result
1634 # from FPIAR and put it in the trace stack frame then jump to _real_trace().
1654 # an exception occurred and that exception was enabled.
1658 # we don't mess with the existing fsave frame. just re-insert it and
1724 # exception occurred from user mode, then simply update a7 and exit normally.
1786 # fmove in and out enter here.
1825 # bit five of the fp extension word separates the monadic and dyadic operations
1872 # fcmp and ftst do not store any result.
1925 and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled & set
1948 # An exception occurred and that exception was enabled:
1976 # as a reminder for future predicted pain and agony, we are passing in fsave the
1977 # "non-skewed" operand for cases of sgl and dbl src INFs,NANs, and DENORMs.
2040 # exception was being traced. Make the "current" PC the FPIAR and put it in the
2069 and.l &0xffff00ff,USER_FPSR(%a6) # zero exception field
2161 and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled
2167 # an exception occurred and that exception was enabled.
2168 # the only exception possible on packed move out are INEX, OPERR, and SNAN.
2409 # _mem_read() "callout", converted to FP binary (if packed), and used #
2412 # emulation, then the result is stored to the destination register and #
2422 # decode and emulate the instruction. No FP exceptions can be pending #
2425 # to a Trace stack frame and an exit made through _real_trace(). #
2432 # Again, a Trace exception may be pending and an exit made through #
2447 # frame. This information includes a faulting address and a fault- #
2457 # So, we must check to see if it's disabled and handle that case separately.
2476 mov.l %d0,EXC_OPWORD(%a6) # store OPWORD and EXTWORD
2584 # now, we're left with ftst and fcmp. so, first let's tag them so that they don't
2585 # store a result. then, only fcmp will branch back and pick up a dst operand.
2649 and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enable and set
2712 # exception was being traced. Make the "current" PC the FPIAR and put it in
2804 # right now, d1 = size and d0 = the strg.
2944 # The FPU is disabled and so we should really have taken the "Line
2962 mov.l %d0,EXC_OPWORD(%a6) # store OPWORD and EXTWORD
2982 # modes and thus can have several different total instruction lengths.
2983 # call fmovm_calc_ea which will go through the ea calc process and,
3091 # for opclass zero and two instruction taking this exception, the #
3093 # and needs to be corrected. This handler calls fix_skewed_ops() to #
3094 # do just this and then exits through _real_operr(). #
3155 # byte, word, and long destination format operations can pass
3157 # operand and save the appropriate minimum or maximum integer value
3281 # for opclass zero and two instructions taking this exception, the #
3283 # and needs to be corrected. This handler calls fix_skewed_ops() to #
3284 # do just this and then exits through _real_snan(). #
3329 # denorm operand in the sgl or dbl format. NANs also become skewed and must be
3351 # byte, word, long, and packed destination format operations can pass
3354 # for byte, word, and long, we simply need to test the sign of the src
3355 # operand and save the appropriate minimum or maximum integer value
3582 # for opclass zero and two instruction taking this exception, the #
3584 # register as did the '040 and '881/2. This handler must emulate the #
3585 # instruction in order to get this value and then store it to the #
3619 # the hardware, for "fabs" and "fneg" w/ a long source format, puts the
3635 # Here, we zero the ccode and exception byte field since we're going to
3653 # bits four and five of the fp extension word separate the monadic and dyadic
3654 # operations that can pass through fpsp_inex(). remember that fcmp and ftst
3716 # byte, word, and long destination format operations can pass
3717 # through here. so can double and single precision.
3762 # be incorrect for some cases and need to be adjusted. So, this package #
3763 # adjusts the operand using fix_skewed_ops() and then branches to #
3833 # This module determines which and forks the flow off to the #
3834 # appropriate "callout" (for "disabled" and "Line F") or to the #
3881 # FP Unimplemented Instruction stack frame and jump to that entry
3934 # load_fop() - load src/dst ops from memory and/or FP regfile #
3962 # unimplemented on the 040, and (2) "ftrapcc", "fscc", and "fdbcc". #
3964 # to load the source and destination (for dyadic) operands to be used #
3966 # chosen by decoding the instruction type and indexing into an #
3974 # exception frame from the current exception frame and exit through #
3976 # For "fdbcc", "ftrapcc", and "fscc", the emulation subroutines #
3977 # _fdbcc(), _ftrapcc(), and _fscc() respectively are used. All three #
3980 # stack frame and an exit is made through _real_bsun(). If the #
3981 # instruction was "ftrapcc" and a Trap exception should result, a Trap #
3982 # exception stack frame is created from the current frame and an exit #
3984 # a Trace exception frame is created from the current frame and a jump #
3990 # is created from the current stack frame and an exit is made through #
4003 # * 0x2 * 0x02c * => frame format and vector offset(vector #11)
4072 # clear the ccode byte and exception status byte
4143 # if the instruction was executed from supervisor mode and the addressing
4181 and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled and set
4186 # and overflow wasn't enabled but inexact was (yech!) then this is
4198 # we'll insert this new exception into the FPU and then return.
4207 # it's actually an inexact and act appropriately. this is the only easy
4256 # These instructions were implemented on the '881/2 and '040 in hardware but
4297 # trap stack frame from an unimplemented fp instruction stack frame and
4388 # restore a bsun exception into the machine, and branch to the user
4424 # and return.
4455 # trace stack frame from an unimplemented fp instruction stack frame and
4976 # from the current frame and branch to _real_access().
5004 # ssincos(): computes the sine and cosine of a normalized input #
5005 # ssincosd(): computes the sine and cosine of a denormalized input #
5018 # ACCURACY and MONOTONICITY ******************************************* #
5026 # SIN and COS: #
5067 # SIN(X) = sgn1 * cos(r) and COS(X) = sgn2*sin(r) where #
5068 # sin(r) and cos(r) are computed as odd and even #
5072 # SIN(X) = sgn1 * sin(r) and COS(X) = sgn1*cos(r) where #
5073 # sin(r) and cos(r) are computed as odd and even #
5078 # 7. (|X|<2**(-40)) SIN(X) = X and COS(X) = 1. Exit. #
5140 and.l &0x7FFFFFFF,%d1 # strip sign
5201 and.l &0x80000000,%d1
5255 and.l &0x80000000,%d1
5261 and.l &0x80000000,%d1
5350 and.l &0x7FFFFFFF,%d1 # COMPACTIFY X
5402 and.l &0x80000000,%d2
5404 and.l &0x80000000,%d2
5414 and.l &0x80000000,%d1
5477 and.l &0x80000000,%d1
5612 and.l &0x00007FFF,%d1
5648 and.l &0x80000000,%d2
5655 #--CREATING 2**(L)*Piby2_1 and 2**(L)*Piby2_2
5670 #--We are now ready to perform (R+r) - N*P1 - N*P2, P1 = 2**(L) * Piby2_1 and
5679 #--Then, we need to compute A := R-P and a := r-p
5723 # ACCURACY and MONOTONICITY ******************************************* #
5738 # 4. (k is even) Tan(X) = tan(r) and tan(r) is approximated by a #
5740 # U = r + r*s*(P1 + s*(P2 + s*P3)), and #
5746 # U = r + r*s*(P1 + s*(P2 + s*P3)), and #
5870 and.l &0x7FFFFFFF,%d1
5898 and.l &0x80000000,%d1 # D0 WAS ODD IFF D0 < 0
6043 and.l &0x00007FFF,%d1
6079 and.l &0x80000000,%d2
6086 #--CREATING 2**(L)*Piby2_1 and 2**(L)*Piby2_2
6101 #--We are now ready to perform (R+r) - N*P1 - N*P2, P1 = 2**(L) * Piby2_1 and
6110 #--Then, we need to compute A := R-P and a := r-p
6153 # ACCURACY and MONOTONICITY ******************************************* #
6353 and.l &0x7FFFFFFF,%d1
6387 and.l &0xF8000000,XFRAC(%a6) # FIRST 5 BITS
6403 and.l &0x00007800,%d1 # 4 VARYING BITS OF F'S FRACTION
6404 and.l &0x7FFF0000,%d2 # EXPONENT OF F
6415 and.l &0x80000000,%d1 # SIGN(F)
6603 # ACCURACY and MONOTONICITY ******************************************* #
6634 and.l &0x7FFFFFFF,%d1
6674 and.l &0x80000000,%d1 # SIGN BIT OF X
6704 # ACCURACY and MONOTONICITY ******************************************* #
6735 and.l &0x7FFFFFFF,%d1
6770 #Returns PI and inexact exception
6800 # ACCURACY and MONOTONICITY ******************************************* #
6806 # ALGORITHM and IMPLEMENTATION **************************************** #
6828 # are the sign and biased exponent field of |X|; the #
6831 # the comparisons in Steps 1.1 and 1.3 can be performed #
6837 # 16380 log(2) and the branch to Step 9 is taken. #
6861 # This error has to be considered later in Steps 3 and 4. #
6868 # Notes: a) The way L1 and L2 are chosen ensures L1+L2 #
6871 # and L1 is no longer than 24 bits. #
6894 # and A5 are single precision; A2 and A3 are double #
6907 # where T and t are the stored values for 2^(J/64). #
6908 # Notes: 2^(J/64) is stored as T and t where T+t approximates #
6910 # and t is in single precision. Note also that T is #
6913 # T-2, and T-8 will all be exact --- a property that will #
6924 # |M| <= 16380, and Scale = 2^M. Moreover, exp(X) will #
6970 # X's sign. "Huge" and "Tiny" are respectively large/tiny #
7005 # 2.5 Create the values Sc = 2^M and #
7022 # and A6 are single precision; A2, A3 and A4 are double #
7035 # where T and t are the stored values for 2^(J/64). #
7036 # Notes: 2^(J/64) is stored as T and t where T+t approximates #
7038 # and t is in single precision. Note also that T is #
7041 # T-2, and T-8 will all be exact --- a property that will #
7070 # precision and rounding modes. To avoid unnecessary #
7081 # precision; and B2 is double extended. #
7088 # X + ( S*B1 + Q ) where S = X*X and #
7103 # Notes: 10.2 will always create an inexact and return -1 + tiny #
7104 # in the user rounding precision and mode. #
7208 #--entry point for EXP(X), here X is finite, non-zero, and not NaN's
7212 and.l &0x7FFF0000,%d1 # biased expo. of X
7219 mov.w 4(%a0),%d1 # expo. and partial sig. of |X|
7238 and.l &0x3F,%d1 # D0 is J = N mod 64
7334 and.l &0x3F,%d1 # D0 is J = N mod 64
7376 and.l &0x7FFF0000,%d1 # biased expo. of X
7384 mov.w 4(%a0),%d1 # expo. and partial sig. of |X|
7402 and.l &0x3F,%d1 # D0 is J = N mod 64
7411 #--a0 points to 2^(J/64), D0 and a1 both contain M
7603 # The exponent bias is removed and the exponent value is #
7609 # an exponent of $3fff and is returned in fp0. The range of #
7681 # ACCURACY and MONOTONICITY ******************************************* #
7693 # y = |X|, z = exp(Y), and #
7710 # Huge*Huge to generate overflow and an infinity with #
7725 and.l &0x7FFFFFFF,%d1
7795 # ACCURACY and MONOTONICITY ******************************************* #
7807 # y = |X|, sgn = sign(X), and z = expm1(Y), #
7825 # sign(X)*Huge*Huge to generate overflow and an infinity with #
7838 and.l &0x7FFFFFFF,%d1
7861 and.l &0x80000000,%d1
7879 and.l &0x80000000,%d1
7913 # ACCURACY and MONOTONICITY ******************************************* #
7925 # sgn := sign(X), y := 2|X|, z := expm1(Y), and #
7964 and.l &0x7FFFFFFF,%d1
7975 and.l &0x7FFF0000,%d1
7978 and.l &0x80000000,SGN(%a6)
8012 and.l &0x7FFF0000,%d1
8015 and.l &0x80000000,SGN(%a6)
8051 and.l &0x80000000,%d1
8054 and.l &0x80000000,%d1
8079 # ACCURACY and MONOTONICITY ******************************************* #
8102 # calculated beforehand and stored in the program. #
8110 # in Step 2 of the algorithm for LOGN and compute #
8365 and.l &0xFE000000,FFRAC(%a6) # FIRST 7 BITS OF Y
8368 and.l &0x7E000000,%d1
8491 #----below), adjusting exponent and storing -k to ADJK
8601 and.l &0xFE000000,FFRAC(%a6)
8612 and.l &0x7E000000,%d1
8630 and.l &0x7E000000,%d1
8674 # ACCURACY and MONOTONICITY ******************************************* #
8694 # 4. (|X| = 1) Generate infinity with an appropriate sign and #
8709 and.l &0x7FFFFFFF,%d1
8723 and.l &0x80000000,%d1
8764 # ACCURACY and MONOTONICITY ******************************************* #
8774 # Step 0. If X < 0, create a NaN and raise the invalid operation #
8777 # traps, and precision control = double extended. #
8788 # Step 0. If X < 0, create a NaN and raise the invalid operation #
8791 # traps, and precision control = double extended. #
8801 # Step 0. If X < 0, create a NaN and raise the invalid operation #
8804 # traps, and precision control = double extended. #
8815 # Step 0. If X < 0, create a NaN and raise the invalid operation #
8818 # traps, and precision control = double extended. #
8880 and.l &0x7FFFFFFF,%d1
8885 and.l &0x00007FFF,%d1
8928 # ACCURACY and MONOTONICITY ******************************************* #
8960 # where L1, L2 are the leading and trailing parts of #
8961 # log_10(2)/64 and L10 is the natural log of 10. Then #
8966 # 1. Fetch 2**(j/64) from table as Fact1 and Fact2. #
8968 # 2. Overwrite Fact1 and Fact2 by #
9097 and.l &0x7FFFFFFF,%d1
9119 and.l &0x3F,%d1 # D0 IS J
9194 and.l &0x7FFFFFFF,%d1
9216 and.l &0x3F,%d1 # D0 IS J
9312 # rounded to the mode and precision specified in d0. #
9449 # answer is inexact, so set INEX2 and AINEX in the user's FPSR.
9607 # the dst is a DENORM. normalize the DENORM and add the adjustment to
9629 # exception to be put into the machine which will be caught and corrected
9671 # Source is outside of 2^14 range. Test the sign and branch
9683 # and set unfl.
9708 # The input operands X and Y can be either normalized or #
9716 # Step 1. Save and strip signs of X and Y: signX := sign(X), #
9751 # Step 8. Return signQ, last 7 bits of Q, and R as required. #
9755 # R := 0. Return signQ, last 7 bits of Q, and R. #
9791 #..Save sign of X and Y
9795 and.l &0x00007FFF,%d3 # Y := |Y|
9842 and.l &0x00008000,%d1
9844 and.l &0x00007FFF,%d0
9903 #..At this point R = 2^(-L)X; Q = 0; k = 0; and k+j = L
9909 cmp.l %d1,%d4 # compare hi(R) and hi(Y)
9911 cmp.l %d2,%d5 # compare lo(R) and lo(Y)
9923 #..and Y < (D1,D2) < 2Y. Either way, perform R - Y
10044 and.l &0x0000007F,%d3 # 7 bits of Q
10045 or.l %d6,%d3 # sign and bits of Q
10048 # and.l &0xFF00FFFF,%d6
10065 # algorithm just got done playing with fp0 and expected no exceptions
10076 #..R = 2^(-j)X - Q Y = Y, thus R = 0 and quotient = 2^j (Q+1)
10095 and.l &0x00000001,%d6
10126 # - Set FPSR exception status dz bit, ccode inf bit, and #
10160 # - For all functions that have a denormalized input and #
10210 # and return the result in fp1.
10344 # we find out if this occurred by doing an fsave and #
10347 # result and EXOP for us. #
10359 # - The inex2 and ainex bits are set. #
10550 # Routine used for fetox, ftwotox, and ftentox. #
10560 # Routine used for flogn, flognp1, flog10, and flog2. #
10640 # cosine register and return a ZERO in fp0 w/ the same sign
10658 # register and jump to the operand error routine for negative
10669 # register and branch to the src QNAN routine.
10679 # in the cosine register and branch to the src SNAN routine.
11356 # Overflow, Underflow, and Unsupported Data Type. #
11376 # frem,fmod, and fscale would get the dst trashed here. But, for
11545 # Handle NANs, infinities, and zeroes as special cases. Divide #
11551 # and return the EXOP if exceptions are enabled. Else, scale the #
11617 # - do the multiply to the proper precision and rounding mode.
11652 # - do the multiply to the proper precision and rounding mode in order to
11654 # - calculate the default result and return it in fp0.
11658 # multiply using extended precision and the correct rounding mode. the result
11736 # - do the multiply to the proper precision and rounding mode in order to
11738 # - calculate the default result and return it in fp0.
11763 # - do the multiply to the proper precision and rounding mode in order to
11765 # - calculate the default result and return it in fp0.
11769 # multiply using extended precision and the correct rounding mode. the result
11849 # -use the correct rounding mode and precision. this code favors operations
12040 # Handle NANs, infinities, and zeroes as special cases. Divide #
12041 # norms into extended, single, and double precision. #
12043 # sgl/dbl, must scale exponent and perform an "fmove". Check to see #
12070 # FP MOVE IN: NORMs and DENORMs ONLY!
12079 # skip the scaling and unscaling...
12107 # the input is an extended DENORM and underflow is enabled in the FPCR.
12108 # normalize the mantissa and add the bias of 0x6000 to the resulting negative
12109 # exponent and insert back into the operand.
12276 # now, round to extended(and don't alter the FPSR).
12317 # operand is not a NORM: check its optype and branch accordingly
12328 # do the fmove in; at this point, only possible ops are ZERO and INF.
12362 # Handle NANs, infinities, and zeroes as special cases. Divide #
12368 # and return the EXOP if exceptions are enabled. Else, scale the #
12407 # DIVIDE: NORMs and DENORMs ONLY!
12748 # The destination was In Range and the source was a ZERO. The result,
12750 # So, determine the sign and return a new INF (w/ the j-bit cleared).
12815 # Handle NANs, zeroes, and infinities as special cases. Separate #
12818 # and an actual fneg performed to see if overflow/underflow would have #
12820 # scale the result exponent and return result. FPSR gets set based on #
12843 # NEGATE SIGN : norms and denorms ONLY!
12852 # skip the scaling and unscaling...
12890 # the input is an extended DENORM and underflow is enabled in the FPCR.
12891 # normalize the mantissa and add the bias of 0x6000 to the resulting negative
12892 # exponent and insert back into the operand.
13056 # now, round to extended(and don't alter the FPSR).
13108 # do the fneg; at this point, only possible ops are ZERO and INF.
13132 # Check the source operand tag (STAG) and set the FPCR according #
13133 # to the operand type and sign. #
13221 # For denorms, force the j-bit to a one and do the same as for #
13269 # also, the INEX2 and AINEX exception bits will be set.
13271 # to a very small NORM and ship it to the NORM routine.
13327 # For denorms, force the j-bit to a one and do the same as for #
13371 # also, the INEX2 and AINEX exception bits will be set.
13373 # to a very small NORM and ship it to the NORM routine.
13433 # Handle NANs, infinities, and zeroes as special cases. Divide #
13434 # norms into extended, single, and double precision. #
13437 # Double and single precision can overflow and underflow. First, #
13443 # result exponent and return. #
13466 # ABSOLUTE VALUE: norms and denorms ONLY!
13475 # skip the scaling and unscaling...
13508 # the input is an extended DENORM and underflow is enabled in the FPCR.
13509 # normalize the mantissa and add the bias of 0x6000 to the resulting negative
13510 # exponent and insert back into the operand.
13671 # now, round to extended(and don't alter the FPSR).
13750 # Handle NANs and denorms as special cases. For everything else, #
13765 # COMPARE FP OPs : NORMs, ZEROs, INFs, and "corrected" DENORMs
13841 # unlike all other functions for QNAN and SNAN, fcmp does NOT set the
13855 # and use the fcmp_norm routine.
13856 # If you have a DENORM and an INF or ZERO, just force the DENORM's j-bit to a one
13857 # and use the fcmp_norm routine.
13858 # If you have a DENORM and a NORM with opposite signs, then use fcmp_norm, also.
13859 # But with a DENORM and a NORM of the same sign, the neg bit is set if the
13860 # (1) signs are (+) and the DENORM is the dst or
13861 # (2) signs are (-) and the DENORM is the src
13947 # Handle NANs, infinities, and zeroes as special cases. Divide #
13953 # and return the EXOP if exceptions are enabled. Else, scale the #
14288 # Handle NANs, infinities, and zeroes as special cases. Divide #
14294 # and return the EXOP if exceptions are enabled. Else, scale the #
14311 # DIVIDE: NORMs and DENORMs ONLY!
14626 # Handle NANs, infinities, and zeroes as special cases. Divide #
14627 # norms into extended, single, and double precision. #
14630 # occurred. If so, return default result and maybe EXOP. Else, insert #
14631 # the correct result exponent and return. Set FPSR bits as appropriate. #
14658 # ADD: norms and denorms
14674 or.l %d1,USER_FPSR(%a6) # save exc and ccode bits
14861 # 0x8000000000000000 and this mantissa is the result of rounding non-zero
14865 # so, we do this be re-executing the add using RZ as the rounding mode and
14967 # and return the appropriately signed zero.
14994 # one operand is a ZERO and the other is a DENORM or NORM. scale
14995 # the DENORM or NORM and jump to the regular fadd routine.
15031 # operands are INF and one of {ZERO, INF, DENORM, NORM}
15041 # operands are INF and one of {ZERO, INF, DENORM, NORM}
15079 # Handle NANs, infinities, and zeroes as special cases. Divide #
15080 # norms into extended, single, and double precision. #
15083 # occurred. If so, return default result and maybe EXOP. Else, insert #
15084 # the correct result exponent and return. Set FPSR bits as appropriate. #
15111 # SUB: norms and denorms
15127 or.l %d1,USER_FPSR(%a6) # save exc and ccode bits
15314 # 0x8000000000000000 and this mantissa is the result of rounding non-zero
15318 # so, we do this be re-executing the add using RZ as the rounding mode and
15446 # one operand is a ZERO and the other is a DENORM or a NORM.
15447 # scale the DENORM or NORM and jump to the regular fsub routine.
15522 # Handle NANs, infinities, and zeroes as special cases. Divide #
15528 # and return the EXOP if exceptions are enabled. Else, scale the #
15552 # SQUARE ROOT: norms and denorms ONLY!
15656 # we're on the line here and the distinguising characteristic is whether
15753 # now, round to extended(and don't alter the FPSR).
15857 # equal to 0x3fff and scale the SRC exponent by the value that the #
15908 and.w &0x8000,%d1
15977 # of the difference between the original and new exponent. Then, #
16031 # to 0x3ffe and return a scale factor of "(exp-0x3ffe)/2". If the #
16032 # exponent of the input operand is off, set the exponent to ox3fff and #
16104 # of the difference between the original and new exponent. Then, #
16163 # enable bit is set in the FPCR, then the trap is taken and the #
16166 # SNAN bit in the operand to one), and the operation continues as #
16265 # the stacked fdbcc instruction opcode and then branches to a routine #
16269 # If a BSUN exception should be indicated, the BSUN and ABSUN #
16272 # enabled BSUN should not be flagged and the predicate is true, then #
16273 # Dn is fetched and decremented by one. If Dn is not equal to -1, add #
16332 # if the NAN bit is set, in which case BSUN and AIOP will be set. #
16334 # The cases EQ and NE are shared by the Aware and Nonaware groups #
16335 # and are incapable of setting the BSUN exception bit. #
16588 # For the IEEE miscellaneous tests, all but fdbf and fdbt can set bsun. #
16869 # the emulation routine set bsun and BSUN was enabled. have to
16870 # fix stack and jump to the bsun handler.
16894 # the stacked ftrapcc instruction opcode and then branches to a routine #
16898 # If a BSUN exception should be indicated, the BSUN and ABSUN #
16901 # enabled BSUN should not be flagged and the predicate is true, then #
16960 # if the NAN bit is set, in which case BSUN and AIOP will be set. #
16962 # The cases EQ and NE are shared by the Aware and Nonaware groups #
16963 # and are incapable of setting the BSUN exception bit. #
17432 # of the ftrapcc instruction and the vector offset field
17438 # the emulation routine set bsun and BSUN was enabled. have to
17439 # fix stack and jump to the bsun handler.
17466 # the stacked fscc instruction opcode and then branches to a routine #
17470 # If a BSUN exception should be indicated, the BSUN and ABSUN #
17473 # enabled BSUN should not be flagged and the predicate is true, then #
17530 # if the NAN bit is set, in which case BSUN and AIOP will be set. #
17532 # The cases EQ and NE are shared by the Aware and Nonaware groups #
17533 # and are incapable of setting the BSUN exception bit. #
18048 # is enabled. if so, don't store result and correct stack frame
18134 # the emulation routine set bsun and BSUN was enabled. have to
18135 # fix stack and jump to the bsun handler.
18143 # and a FSLW to funimp_dacc().
18181 # The data register is determined and its value loaded to get the #
18186 # to read in all FP values. Again, _mem_read() may fail and require a #
18191 # then we return the size of the dump and the string to the caller #
18236 # but, make sure that we've calculated ea and advanced the opword pointer
18253 # operations and postincrement mode. (bit7 = FP7 ... bit0 = FP0)
18266 # we're also passing "size" and "strg" back to the calling routine
18526 # currently, MODE and REG are taken from the EXC_OPWORD. this could be
19349 # The stacked <ea> for FP unimplemented instructions and opclass #
19353 # Also, for extended precision and packed, the #
19357 # stacked b,w,l and s sizes are completely stacked. #
19358 # d,x, and p are not. #
19402 # the <ea> is stacked correctly for all but extended and packed which
19423 # and packed data opclass 3 operations. #
19435 # For opclass 3 extended and packed data operations, the <ea> #
19436 # stacked for the exception is incorrect for -(an) and (an)+ addressing #
19440 # and return that value as the correct <ea> and store that value in An. #
19446 # for fmove outs of type extended and packed.
19464 # (An)+ : extended and packed fmove out
19509 # -(An) : extended and packed fmove out
19585 # order to load the source and maybe destination operand into #
19586 # FP_SRC(a6) and FP_DST(a6). If the instruction was opclass zero, load #
19587 # the source and destination from the FP register file. Set the optype #
19591 # the destination from the register file and the source operand from #
19592 # memory. Tag and fix both as above w/ opclass zero instructions. #
19599 # Immediate data and regular data accesses are separated because #
19634 and.w &0x007f,%d0 # extract extension bits {6:0}
19677 and.w &0x007f,%d0 # extract extension bits {6:0}
19762 # separate SNANs and DENORMs so they can be loaded w/ special care.
19994 lsl.l &0x8, %d0 # extract and insert hi(man)
20184 # either occurs and is enabled, the EXOP. #
20187 # the source is a denorm and if underflow is enabled, an EXOP must be #
20382 # the stack frame. so, leave it in FP_SRC for now and deal with it later...
20441 # separately. otherwise, set the FPCR to the proper rounding mode and
20463 fmov.s %fp0,%d0 # store does convert and round
20491 # so, denorm and round and then use generic store single routine to
20558 # call ovf_res() w/ sgl prec and the correct rnd mode to create the default
20679 # separately. otherwise, set the FPCR to the proper rounding mode and
20701 fmov.d %fp0,L_SCR1(%a6) # store does convert and round
20720 # so, denorm and round and then use generic store double routine to
20779 # call ovf_res() w/ dbl prec and the correct rnd mode to create the default
20949 lsr.l &0x8,%d1 # and put them flush right
21694 # mantissa bits right, maintain the value of the guard, round, and #
21713 # Load the exponent threshold for the precision selected and check
21715 # simply calculate the sticky bit and zero the mantissa. otherwise
21736 # calculate if the sticky should be set and clear the entire mantissa.
21765 # make a copy of FTEMP_LO and place the g,r,s bits directly after it
21839 and.l &0xe0000000, %d0 # clear all but G,R,S
21870 subi.w &0x20, %d1 # %d1 now between 0 and 32
21898 and.l &0xe0000000, %d0 # clear all but G,R,S
21919 # Shift value is > 65 and out of range. All bits are shifted off.
21950 and.l &0xc0000000, %d0 # extract G,R
21951 and.l &0x3fffffff, %d1 # extract other bits
21977 and.l &0x80000000, %d0 # extract R bit
21979 and.l &0x7fffffff, %d1 # extract other bits
21982 # last operation done was an "and" of the bits shifted off so the condition
21992 # the guard and
22034 # a0 is preserved and the g-r-s bits in d0 are cleared. #
22046 # ext_grs() looks at the rounding precision and sets the appropriate
22048 # If (G,R,S == 0) then result is exact and round is done, else set
22049 # the inex flag in status reg and continue.
22108 # If (g=1), then add 1 to l and if (r=s=0), then clear l #
22134 add.w &0x1, FTEMP_EX(%a0) # and incr exponent
22138 and.w &0xfe00, FTEMP_HI+2(%a0) # clear the l-bit
22140 and.l &0xffffff00, FTEMP_HI(%a0) # truncate bits beyond sgl limit
22156 add.w &0x1,FTEMP_EX(%a0) # and inc exp
22160 and.b &0xfe,FTEMP_LO+3(%a0) # clear the l bit
22181 and.w &0xf000, FTEMP_LO+2(%a0) # clear the l-bit
22184 and.l &0xfffff800,FTEMP_LO(%a0) # truncate bits beyond dbl limit
22200 # ext_grs(): extract guard, round and sticky bits according to
22214 # Notes: the ext_grs uses the round PREC, and therefore has to swap d1
22215 # prior to usage, and needs to restore d1 to original. this
22216 # routine is tightly tied to the round routine and not meant to
22256 and.l &0x0000003f, %d2 # s bit is the or of all other
22262 bra.b ext_grs_end_sd # if words 3 and 4 are clr, exit
22281 and.l &0x000001ff, %d2 # s bit is the or-ing of all
22375 # zero; both the exponent and mantissa are changed. #
22399 and.w &0x7fff, %d1 # strip off sgn
22409 and.w &0x8000, %d0 # save old sign
22432 and.w &0x8000, FTEMP_EX(%a0) # set exp = 0
22449 and.w &0x8000, FTEMP_EX(%a0) # set exp = 0
22458 and.w &0x8000, FTEMP_EX(%a0) # force exponent to zero
22478 # Simply test the exponent, j-bit, and mantissa values to #
22480 # If it's an unnormalized zero, alter the operand and force it #
22529 and.l &0x7fffffff, %d0 # msb is a don't care!
22558 # Simply test the exponent, j-bit, and mantissa values to #
22578 and.l &0x000fffff, %d1
22589 and.l &0x000fffff, %d1
22621 # Simply test the exponent, j-bit, and mantissa values to #
22641 and.l &0x007fffff, %d1
22650 and.l &0x007fffff, %d1
22671 # single round prec and extended prec mode. #
22688 # exponent is extended to 16 bits and the sign is stored in the unused #
22696 # precision and the rounding mode to single. #
22707 and.w &0x7fff, %d1
22750 # can inex1 also be set along with unfl and inex2???
22762 # unf_res() for fsglmul() and fsgldiv().
22771 and.w &0x7fff,%d1
22810 # can inex1 also be set along with unfl and inex2???
22846 # the result and the rounding mode/prec in effect. These bits are #
22865 and.w &0x10, %d1 # keep result sign
22873 # use the rounding mode, precision, and result sign as in index into the
22874 # two tables below to fetch the default result and the result ccodes.
22929 # get_packed(): fetch a packed operand from memory and then #
22957 # the base reg must be updated for both -(An) and (An)+.
23005 # and NaN operands are dispatched without entering this routine) #
23008 # A1. Convert the bcd exponent to binary by successive adds and #
23011 # digits, rather than 1 integer and 16 fraction digits. #
23015 # adds and muls in FP0. Set the sign according to SM. #
23023 # exponent equal to the exponent from A1 and the zero count #
23024 # added if SM = 1 and subtracted if SM = 0. Scale the #
23037 # tables rounded to RN, RM, and RP, according to the table #
23043 # exponent sign is positive, and dividing FP0 by FP1 if #
23046 # Clean up and return. Check if the final mul or div was inexact. #
23052 # PTENRN, PTENRM, and PTENRP are arrays of powers of 10 rounded
23053 # to nearest, minus, and plus, respectively. The tables include
23083 # 2. Calculate absolute value of exponent in d1 by mul and add.
23108 bfextu %d4{%d3:&4},%d0 # get the digit and zero extend into d0
23118 neg.l %d1 # now negative, make pos and set SE
23120 or.l &0x40000000,(%a0) # and in working bcd
23126 # 1. Calculate absolute value of mantissa in fp0 by mul and add.
23137 # ( ) d4: words 2 and 3 of bcd
23165 bfextu %d4{%d3:&4},%d0 # get the digit and zero extend
23170 # then inc d1 (=2) to point to the next long word and reset d3 to 0
23171 # to initialize the digit offset, and set d2 to 7 for the digit count;
23181 # Check the sign of the mant and make the value in fp0 the same sign.
23193 # if the exp was positive, and added if it was negative. The purpose
23194 # of this is to reduce the value of the exponent and the possibility
23199 # 2. Check M16 and the digits in lwords 2 and 3 in descending order.
23203 # and set SE.
23206 # 2. Check the digits in lwords 3 and 2 in descending order.
23234 # and do append (+) or strip (-) zeros accordingly.
23251 addq.l &8,%d1 # and inc count by 8
23270 or.l &0x40000000,%d4 # and set SE in d4
23271 or.l &0x40000000,(%a0) # and in memory
23316 neg.l %d1 # take abs of exp and clr SE
23318 and.l &0xbfffffff,%d4 # and clr SE in d4
23319 and.l &0xbfffffff,(%a0) # and in memory
23340 # Calculate power-of-ten factor from adjusted and shifted exponent.
23391 clr.l %d3 # clear d3 to force no exc and extended
23409 or.l &0x40000000,(%a0) # and set SE bit
23423 # Check the sign of the adjusted exp and make the value in fp0 the
23443 # Clean up and return with result in fp0.
23450 bclr &inex2_bit+8,%d0 # test for inex2 and clear it
23475 # A1. Set RM and size ext; Set SIGMA = sign of input. #
23511 # function of the original rounding mode and the signs #
23512 # of ISCALE and X. A table is given in the code. #
23540 # or less than LEN -1 digits, adjust ILOG and repeat from #
23542 # result is exactly 10^LEN, decrement ILOG and divide #
23548 # to be a fraction; i.e. (mantissa)/10^LEN and adjusted #
23554 # As in A14 above, the exp is converted to bcd and the #
23615 # A1. Set RM and size ext. Set SIGMA = sign input;
23620 # the input and test for denormalized result.
23622 fmov.l &rm_mode*0x10,%fpcr # set RM and ext
23635 and.w &0x7fff,%d0 # strip sign of normalized exp
23651 and.w &0x7fff,%d0 # strip sign of normalized exp
23662 and.l &0x7fffffff,FP_SCR1(%a6) # create abs(X)
23826 bgt.b k_pos # if pos and > 0, skip this
23845 neg.l %d0 # and take abs of ISCALE
23902 # with a multiply by 10^8 and 10^16, which is exact since
23904 # create a busy stack frame with the mul command and the
23905 # two operands, and allow the fpu to complete the multiply.
23942 # so, we do the multiplication of the exponents and mantissas separately.
23944 # multiplication and guarantee a result without exception.
24025 # mode and precision. The original FPCR is saved in L_SCR1.
24029 and.l &0x00000030,USER_FPCR(%a6) # set size to ext,
24048 # a6: temp pointer to FP_SCR1(a6) - orig value saved and restored
24095 # or less than LEN -1 digits, adjust ILOG and repeat from
24097 # result is exactly 10^LEN, decrement ILOG and divide
24144 # 10^LEN-1 is computed for this test and A14. If the input was
24152 # Compare abs(YINT) to 10^(LEN-1) and 10^LEN
24162 bra.w A6_str # return to A6 and recompute YINT
24167 fbgt.w fix_ex # if greater, fix and redo
24169 addq.l &1,%d6 # and inc ILOG
24170 bra.b A14_st # and continue elsewhere
24175 bra.w A6_str # return to A6 and recompute YINT
24178 # and shouldn't have another; this is to check if abs(YINT) = 10^LEN
24198 addq.l &1,%d6 # and inc ILOG by 1
24199 addq.l &1,%d4 # and inc LEN
24205 # to be a fraction; i.e. (mantissa)/10^LEN and adjusted
24262 and.l &0xffffff80,%d3 # strip off lsb not used by 882
24270 # As in A14 above, the exp is converted to bcd and the
24347 and.l &0xffffff80,%d3 # strip off lsb not used by 882
24387 and.b &0x0f,FP_SCR0(%a6) # clear first nibble of FP_SCR0
24396 bfins %d0,FP_SCR0(%a6){&0:&2} # insert SM and SE into FP_SCR0
24398 # Clean up and restore all registers used.
24469 # shift and a mul by 8 shift. The bits shifted out of the #
24473 # A1. Init d7 to 1. D7 is the byte digit counter, and if 1, the #
24481 # extracts and shifts. The three msbs from d2 will go into d1. #
24486 # A5. Add using the carry the 64-bit quantities in d2:d3 and d4:d5 #
24494 # A7. Decrement d6 (LEN counter) and repeat the loop until zero. #
24553 # A6. Test d7 and branch.
24576 # Clean up and return with result in fp0.
24610 # -(an)+ register gets returned to its pre-exception value and then #
24767 # instruction (data moved in) and the exception was in supervisor