arm64/kvm/vgic-sys-reg-v3.c

18 	struct vgic_vmcr vmcr;
20 	vgic_get_vmcr(vcpu, &vmcr);
52 	vmcr.cbpr = FIELD_GET(ICC_CTLR_EL1_CBPR_MASK, val);
53 	vmcr.eoim = FIELD_GET(ICC_CTLR_EL1_EOImode_MASK, val);
54 	vgic_set_vmcr(vcpu, &vmcr);
63 	struct vgic_vmcr vmcr;
66 	vgic_get_vmcr(vcpu, &vmcr);
79 	val |= FIELD_PREP(ICC_CTLR_EL1_CBPR_MASK, vmcr.cbpr);
80 	val |= FIELD_PREP(ICC_CTLR_EL1_EOImode_MASK, vmcr.eoim);
90 	struct vgic_vmcr vmcr;
92 	vgic_get_vmcr(vcpu, &vmcr);
93 	vmcr.pmr = FIELD_GET(ICC_PMR_EL1_MASK, val);
94 	vgic_set_vmcr(vcpu, &vmcr);
102 	struct vgic_vmcr vmcr;
104 	vgic_get_vmcr(vcpu, &vmcr);
105 	*val = FIELD_PREP(ICC_PMR_EL1_MASK, vmcr.pmr);
113 	struct vgic_vmcr vmcr;
115 	vgic_get_vmcr(vcpu, &vmcr);
116 	vmcr.bpr = FIELD_GET(ICC_BPR0_EL1_MASK, val);
117 	vgic_set_vmcr(vcpu, &vmcr);
125 	struct vgic_vmcr vmcr;
127 	vgic_get_vmcr(vcpu, &vmcr);
128 	*val = FIELD_PREP(ICC_BPR0_EL1_MASK, vmcr.bpr);
136 	struct vgic_vmcr vmcr;
138 	vgic_get_vmcr(vcpu, &vmcr);
139 	if (!vmcr.cbpr) {
140 		vmcr.abpr = FIELD_GET(ICC_BPR1_EL1_MASK, val);
141 		vgic_set_vmcr(vcpu, &vmcr);
150 	struct vgic_vmcr vmcr;
152 	vgic_get_vmcr(vcpu, &vmcr);
153 	if (!vmcr.cbpr)
154 		*val = FIELD_PREP(ICC_BPR1_EL1_MASK, vmcr.abpr);
156 		*val = min((vmcr.bpr + 1), 7U);
165 	struct vgic_vmcr vmcr;
167 	vgic_get_vmcr(vcpu, &vmcr);
168 	vmcr.grpen0 = FIELD_GET(ICC_IGRPEN0_EL1_MASK, val);
169 	vgic_set_vmcr(vcpu, &vmcr);
177 	struct vgic_vmcr vmcr;
179 	vgic_get_vmcr(vcpu, &vmcr);
180 	*val = FIELD_PREP(ICC_IGRPEN0_EL1_MASK, vmcr.grpen0);
188 	struct vgic_vmcr vmcr;
190 	vgic_get_vmcr(vcpu, &vmcr);
191 	vmcr.grpen1 = FIELD_GET(ICC_IGRPEN1_EL1_MASK, val);
192 	vgic_set_vmcr(vcpu, &vmcr);
200 	struct vgic_vmcr vmcr;
202 	vgic_get_vmcr(vcpu, &vmcr);
203 	*val = FIELD_GET(ICC_IGRPEN1_EL1_MASK, vmcr.grpen1);