Lines Matching defs:rd
112 static u32 compute_instruction(int n, u32 rd, u32 rn)
120 rn, rd, va_mask);
126 rn, rn, rd,
131 insn = aarch64_insn_gen_add_sub_imm(rd, rn,
138 insn = aarch64_insn_gen_add_sub_imm(rd, rn,
147 rn, rn, rd, 64 - tag_lsb);
162 u32 rd, rn, insn, oinsn;
178 rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, oinsn);
181 insn = compute_instruction(i, rd, rn);
246 u32 insn, oinsn, rd;
252 rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, oinsn);
254 /* movz rd, #(val & 0xffff) */
255 insn = aarch64_insn_gen_movewide(rd,
262 /* movk rd, #((val >> 16) & 0xffff), lsl #16 */
263 insn = aarch64_insn_gen_movewide(rd,
270 /* movk rd, #((val >> 32) & 0xffff), lsl #32 */
271 insn = aarch64_insn_gen_movewide(rd,
278 /* movk rd, #((val >> 48) & 0xffff), lsl #48 */
279 insn = aarch64_insn_gen_movewide(rd,