kvm/hyp/vgic-v3-sr.c

463 static void __vgic_v3_write_vmcr(u32 vmcr)
465 	write_gicreg(vmcr, ICH_VMCR_EL2);
503 static int __vgic_v3_highest_priority_lr(struct kvm_vcpu *vcpu, u32 vmcr,
519 		if (!(val & ICH_LR_GROUP) && !(vmcr & ICH_VMCR_ENG0_MASK))
523 		if ((val & ICH_LR_GROUP) && !(vmcr & ICH_VMCR_ENG1_MASK))
594 static unsigned int __vgic_v3_get_bpr0(u32 vmcr)
596 	return (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
599 static unsigned int __vgic_v3_get_bpr1(u32 vmcr)
603 	if (vmcr & ICH_VMCR_CBPR_MASK) {
604 		bpr = __vgic_v3_get_bpr0(vmcr);
608 		bpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
618 static u8 __vgic_v3_pri_to_pre(u8 pri, u32 vmcr, int grp)
623 		bpr = __vgic_v3_get_bpr0(vmcr) + 1;
625 		bpr = __vgic_v3_get_bpr1(vmcr);
636 static void __vgic_v3_set_active_priority(u8 pri, u32 vmcr, int grp)
642 	pre = __vgic_v3_pri_to_pre(pri, vmcr, grp);
693 static void __vgic_v3_read_iar(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
701 	lr = __vgic_v3_highest_priority_lr(vcpu, vmcr, &lr_val);
708 	pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
713 	if (__vgic_v3_get_highest_active_priority() <= __vgic_v3_pri_to_pre(lr_prio, vmcr, grp))
719 	__vgic_v3_set_active_priority(lr_prio, vmcr, grp);
749 static void __vgic_v3_write_dir(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
756 	if (!(vmcr & ICH_VMCR_EOIM_MASK))
772 static void __vgic_v3_write_eoir(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
793 	if ((vmcr & ICH_VMCR_EOIM_MASK) && !(vid >= VGIC_MIN_LPI))
800 	    __vgic_v3_pri_to_pre(lr_prio, vmcr, grp) != act_prio)
807 static void __vgic_v3_read_igrpen0(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
809 	vcpu_set_reg(vcpu, rt, !!(vmcr & ICH_VMCR_ENG0_MASK));
812 static void __vgic_v3_read_igrpen1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
814 	vcpu_set_reg(vcpu, rt, !!(vmcr & ICH_VMCR_ENG1_MASK));
817 static void __vgic_v3_write_igrpen0(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
822 		vmcr |= ICH_VMCR_ENG0_MASK;
824 		vmcr &= ~ICH_VMCR_ENG0_MASK;
826 	__vgic_v3_write_vmcr(vmcr);
829 static void __vgic_v3_write_igrpen1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
834 		vmcr |= ICH_VMCR_ENG1_MASK;
836 		vmcr &= ~ICH_VMCR_ENG1_MASK;
838 	__vgic_v3_write_vmcr(vmcr);
841 static void __vgic_v3_read_bpr0(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
843 	vcpu_set_reg(vcpu, rt, __vgic_v3_get_bpr0(vmcr));
846 static void __vgic_v3_read_bpr1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
848 	vcpu_set_reg(vcpu, rt, __vgic_v3_get_bpr1(vmcr));
851 static void __vgic_v3_write_bpr0(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
862 	vmcr &= ~ICH_VMCR_BPR0_MASK;
863 	vmcr |= val;
865 	__vgic_v3_write_vmcr(vmcr);
868 static void __vgic_v3_write_bpr1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
873 	if (vmcr & ICH_VMCR_CBPR_MASK)
882 	vmcr &= ~ICH_VMCR_BPR1_MASK;
883 	vmcr |= val;
885 	__vgic_v3_write_vmcr(vmcr);
911 					    u32 vmcr, int rt)
917 					    u32 vmcr, int rt)
922 static void __vgic_v3_read_apxr2(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
927 static void __vgic_v3_read_apxr3(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
932 static void __vgic_v3_write_apxr0(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
937 static void __vgic_v3_write_apxr1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
942 static void __vgic_v3_write_apxr2(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
947 static void __vgic_v3_write_apxr3(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
952 static void __vgic_v3_read_hppir(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
959 	lr = __vgic_v3_highest_priority_lr(vcpu, vmcr, &lr_val);
971 static void __vgic_v3_read_pmr(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
973 	vmcr &= ICH_VMCR_PMR_MASK;
974 	vmcr >>= ICH_VMCR_PMR_SHIFT;
975 	vcpu_set_reg(vcpu, rt, vmcr);
978 static void __vgic_v3_write_pmr(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
984 	vmcr &= ~ICH_VMCR_PMR_MASK;
985 	vmcr |= val;
987 	write_gicreg(vmcr, ICH_VMCR_EL2);
990 static void __vgic_v3_read_rpr(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
996 static void __vgic_v3_read_ctlr(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
1011 	val |= ((vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT) << ICC_CTLR_EL1_EOImode_SHIFT;
1013 	val |= (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
1018 static void __vgic_v3_write_ctlr(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
1023 		vmcr |= ICH_VMCR_CBPR_MASK;
1025 		vmcr &= ~ICH_VMCR_CBPR_MASK;
1028 		vmcr |= ICH_VMCR_EOIM_MASK;
1030 		vmcr &= ~ICH_VMCR_EOIM_MASK;
1032 	write_gicreg(vmcr, ICH_VMCR_EL2);
1039 	u32 vmcr;
1155 	vmcr = __vgic_v3_read_vmcr();
1157 	fn(vcpu, vmcr, rt);