arm64/kernel/cpufeature.c

26  * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch
43  * - A "feature" is typically a 4-bit register field. A "capability" is the
1035 		if (WARN(caps->capability >= ARM64_NCAPS,
1036 			"Invalid capability %d\n", caps->capability))
1038 		if (WARN(cpucap_ptrs[caps->capability],
1039 			"Duplicate entry for capability %d\n",
1040 			caps->capability))
1042 		cpucap_ptrs[caps->capability] = caps;
2036 	 * unconditionally enable the capability to allow any late CPU
2087 	 * the capability to allow any late CPU to use the feature.
2181 	 * a chance to update the state, with the capability.
2342 /* Internal helper functions to match cpu capability type */
2363 		.capability = ARM64_ALWAYS_BOOT,
2368 		.capability = ARM64_ALWAYS_SYSTEM,
2374 		.capability = ARM64_HAS_GIC_CPUIF_SYSREGS,
2381 		.capability = ARM64_HAS_ECV,
2388 		.capability = ARM64_HAS_ECV_CNTPOFF,
2396 		.capability = ARM64_HAS_PAN,
2406 		.capability = ARM64_HAS_EPAN,
2415 		.capability = ARM64_HAS_LSE_ATOMICS,
2423 		.capability = ARM64_HAS_VIRT_HOST_EXTN,
2430 		.capability = ARM64_HAS_NESTED_VIRT,
2436 		.capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE,
2444 		.capability = ARM64_HAS_32BIT_EL1,
2451 		.capability = ARM64_KVM_PROTECTED_MODE,
2457 		.capability = ARM64_HAS_HCX,
2465 		.capability = ARM64_UNMAP_KERNEL_AT_EL0,
2477 		.capability = ARM64_HAS_FPSIMD,
2486 		.capability = ARM64_HAS_DCPOP,
2493 		.capability = ARM64_HAS_DCPODP,
2503 		.capability = ARM64_SVE,
2512 		.capability = ARM64_HAS_RAS_EXTN,
2522 		.capability = ARM64_HAS_AMU_EXTN,
2532 		.capability = ARM64_HAS_CACHE_IDC,
2539 		.capability = ARM64_HAS_CACHE_DIC,
2546 		.capability = ARM64_HAS_STAGE2_FWB,
2553 		.capability = ARM64_HAS_ARMv8_4_TTL,
2559 		.capability = ARM64_HAS_TLB_RANGE,
2568 		.capability = ARM64_HW_DBM,
2577 		.capability = ARM64_HAS_CRC32,
2584 		.capability = ARM64_SSBS,
2592 		.capability = ARM64_HAS_CNP,
2601 		.capability = ARM64_HAS_SB,
2609 		.capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5,
2616 		.capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3,
2623 		.capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
2629 		.capability = ARM64_HAS_ADDRESS_AUTH,
2635 		.capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5,
2642 		.capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3,
2649 		.capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
2655 		.capability = ARM64_HAS_GENERIC_AUTH,
2666 		.capability = ARM64_HAS_GIC_PRIO_MASKING,
2674 		.capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC,
2682 		.capability = ARM64_HAS_E0PD,
2691 		.capability = ARM64_HAS_RNG,
2699 		.capability = ARM64_BTI,
2713 		.capability = ARM64_MTE,
2721 		.capability = ARM64_MTE_ASYMM,
2729 		.capability = ARM64_HAS_LDAPR,
2737 		.capability = ARM64_HAS_FGT,
2745 		.capability = ARM64_SME,
2750 	/* FA64 should be sorted after the base SME capability */
2754 		.capability = ARM64_SME_FA64,
2762 		.capability = ARM64_SME2,
2770 		.capability = ARM64_HAS_WFXT,
2777 		.capability = ARM64_HAS_TIDCP1,
2785 		.capability = ARM64_HAS_DIT,
2793 		.capability = ARM64_HAS_MOPS,
2800 		.capability = ARM64_HAS_TCR2,
2807 		.capability = ARM64_HAS_S1PIE,
2814 		.capability = ARM64_KVM_HVHE,
2820 		.capability = ARM64_HAS_EVT,
2827 		.capability = ARM64_HAS_LPA2,
2834 		.capability = ARM64_HAS_FPMR,
2841 		.capability = ARM64_HAS_VA52,
2859 		.capability = ARM64_HAS_HCR_NV1,
3140 		    cpus_have_cap(caps->capability) ||
3147 		__set_bit(caps->capability, system_cpucaps);
3150 			set_bit(caps->capability, boot_cpucaps);
3194 		    !cpus_have_cap(caps->capability))
3201 			 * will enable the capability as appropriate via
3203 			 * the boot CPU, for which the capability must be
3223  * If the system has already detected a capability, take necessary
3240 		system_has_cap = cpus_have_cap(caps->capability);
3259 			 * Check if the CPU has this capability if it isn't
3268 		pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
3269 			smp_processor_id(), caps->capability,
3370  * Any new CPU should match the system wide status of the capability. If the
3371  * new CPU doesn't have a capability which the system now has enabled, we