arm64/kernel/cpufeature.c

16  * boot CPU and comparing these with the feature registers of each secondary
408 	 * We already refuse to boot CPUs that don't support our configured
1184 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
1192 	if ((boot & regp->strict_mask) == (val & regp->strict_mask))
1195 			regp->name, boot, cpu, val);
1219 					 struct cpuinfo_arm64 *boot)
1226 	if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0))
1229 	boot->aarch32 = info->aarch32;
1230 	init_32bit_cpu_features(&boot->aarch32);
1235 				     struct cpuinfo_32bit *boot)
1254 				      info->reg_id_dfr0, boot->reg_id_dfr0);
1256 				      info->reg_id_dfr1, boot->reg_id_dfr1);
1258 				      info->reg_id_isar0, boot->reg_id_isar0);
1260 				      info->reg_id_isar1, boot->reg_id_isar1);
1262 				      info->reg_id_isar2, boot->reg_id_isar2);
1264 				      info->reg_id_isar3, boot->reg_id_isar3);
1266 				      info->reg_id_isar4, boot->reg_id_isar4);
1268 				      info->reg_id_isar5, boot->reg_id_isar5);
1270 				      info->reg_id_isar6, boot->reg_id_isar6);
1278 				      info->reg_id_mmfr0, boot->reg_id_mmfr0);
1280 				      info->reg_id_mmfr1, boot->reg_id_mmfr1);
1282 				      info->reg_id_mmfr2, boot->reg_id_mmfr2);
1284 				      info->reg_id_mmfr3, boot->reg_id_mmfr3);
1286 				      info->reg_id_mmfr4, boot->reg_id_mmfr4);
1288 				      info->reg_id_mmfr5, boot->reg_id_mmfr5);
1290 				      info->reg_id_pfr0, boot->reg_id_pfr0);
1292 				      info->reg_id_pfr1, boot->reg_id_pfr1);
1294 				      info->reg_id_pfr2, boot->reg_id_pfr2);
1296 				      info->reg_mvfr0, boot->reg_mvfr0);
1298 				      info->reg_mvfr1, boot->reg_mvfr1);
1300 				      info->reg_mvfr2, boot->reg_mvfr2);
1307  * non-boot CPU. Also performs SANITY checks to make sure that there
1308  * aren't any insane variations from that of the boot CPU.
1312 			 struct cpuinfo_arm64 *boot)
1322 				      info->reg_ctr, boot->reg_ctr);
1330 				      info->reg_dczid, boot->reg_dczid);
1334 				      info->reg_cntfrq, boot->reg_cntfrq);
1343 				      info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
1345 				      info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
1351 				      info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
1353 				      info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
1355 				      info->reg_id_aa64isar2, boot->reg_id_aa64isar2);
1357 				      info->reg_id_aa64isar3, boot->reg_id_aa64isar3);
1365 				      info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
1367 				      info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
1369 				      info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
1371 				      info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3);
1374 				      info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
1376 				      info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
1378 				      info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2);
1381 				      info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
1384 				      info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0);
1387 				      info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0);
1427 					      info->reg_gmid, boot->reg_gmid);
1439 		lazy_init_32bit_cpu_features(info, boot);
1441 						   &boot->aarch32);
2176 	 * CPUs with that of the boot CPU. The level of boot cpu is fetched
2180 	 * boot CPU as a mismatched secondary CPU is parked before it gets
2227 	 * ARM64_HAS_GIC_CPUIF_SYSREGS has a lower index, and is a boot CPU
2246 	 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU
3211 			 * the boot CPU, for which the capability must be
3219 	 * For all non-boot scope capabilities, use stop_machine()
3288  * Check for CPU features that are used in early boot
3377  * The capabilities were decided based on the available CPUs at the boot time.
3407 	 * in use by the kernel based on boot CPU.
3481 	 * The boot CPU's feature register values have been recorded. Detect
3482 	 * boot cpucaps and local cpucaps for the boot CPU, then enable and
3483 	 * patch alternatives for the available boot cpucaps.
3494 	 * handle the boot CPU.