Lines Matching defs:x2
68 csel x2, xzr, x0, lt // all PMU counters from EL1
82 orr x2, x2, x0 // If we don't have VHE, then
95 orr x2, x2, x0 // allow the EL1&0 translation
99 msr mdcr_el2, x2 // Configure debug traps
217 * Regs: x0, x1 and x2 are clobbered.
272 check_override id_aa64pfr0, ID_AA64PFR0_EL1_SVE_SHIFT, .Linit_sve_\@, .Lskip_sve_\@, x1, x2
293 check_override id_aa64pfr1, ID_AA64PFR1_EL1_SME_SHIFT, .Linit_sme_\@, .Lskip_sme_\@, x1, x2
320 __check_override id_aa64smfr0, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, .Linit_sme_fa64_\@, .Lskip_sme_fa64_\@, x1, x2
328 __check_override id_aa64smfr0, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, .Linit_sme_zt0_\@, .Lskip_sme_zt0_\@, x1, x2