Lines Matching refs:c6
57 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
115 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
197 2: mcr p15, 0, r3, c7, c6, 2 @ flush D entry
247 mcr p15, 0, r3, c7, c6, 2 @ invalidate D entry
285 mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
288 mcr p15, 0, r0, c6, c3, 0 @ disable data area 3~7
289 mcr p15, 0, r0, c6, c4, 0
290 mcr p15, 0, r0, c6, c5, 0
291 mcr p15, 0, r0, c6, c6, 0
292 mcr p15, 0, r0, c6, c7, 0
294 mcr p15, 0, r0, c6, c3, 1 @ disable instruction area 3~7
295 mcr p15, 0, r0, c6, c4, 1
296 mcr p15, 0, r0, c6, c5, 1
297 mcr p15, 0, r0, c6, c6, 1
298 mcr p15, 0, r0, c6, c7, 1
301 mcr p15, 0, r0, c6, c0, 0 @ set area 0, default
302 mcr p15, 0, r0, c6, c0, 1
307 mcr p15, 0, r3, c6, c1, 0 @ set area 1, RAM
308 mcr p15, 0, r3, c6, c1, 1
313 mcr p15, 0, r3, c6, c2, 0 @ set area 2, ROM/FLASH
314 mcr p15, 0, r3, c6, c2, 1