Lines Matching refs:r5
300 mov32 r5, TEGRA_CLK_RESET_BASE
443 adr r5, tegra_sdram_pad_save
445 ldr r4, [r5, #0x18] @ restore CLK_SOURCE_MSELECT
448 ldr r4, [r5, #0x1C] @ restore SCLK_BURST
456 ldr r1, [r5, #0x14] @ PMC_IO_DPD_STATUS
473 ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL
475 ldr r1, [r5, #0x10] @ restore EMC_XM2VTTGENPADCTRL2
477 ldr r1, [r5, #0x8] @ restore EMC_AUTO_CAL_INTERVAL
568 ldr r1, [r5, #0x4] @ restore EMC_ZCAL_INTERVAL
570 ldr r1, [r5, #0x0] @ restore EMC_CFG
581 addne r5, r5, #0x20
661 * r5 = TEGRA_CLK_RESET_BASE
672 str r0, [r5, #CLK_RESET_SCLK_BURST]
677 str r0, [r5, #CLK_RESET_CCLK_BURST]
679 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
680 str r0, [r5, #CLK_RESET_SCLK_DIVIDER]
683 ldr r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
685 str r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
693 store_pll_state r0, r1, r5, CLK_RESET_PLLA_BASE, PLLA_STORE_MASK
694 store_pll_state r0, r1, r5, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK
695 store_pll_state r0, r1, r5, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK
696 store_pll_state r0, r1, r5, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK
697 store_pll_state r0, r1, r5, CLK_RESET_PLLX_BASE, PLLX_STORE_MASK
708 ldr r0, [r5, #CLK_RESET_PLLP_BASE]
711 str r0, [r5, #CLK_RESET_PLLP_BASE]
714 str r0, [r5, #CLK_RESET_PLLP_RESHIFT]
716 ldr r0, [r5, #CLK_RESET_PLLA_BASE]
718 str r0, [r5, #CLK_RESET_PLLA_BASE]
719 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
721 str r0, [r5, #CLK_RESET_PLLC_BASE]
722 ldr r0, [r5, #CLK_RESET_PLLX_BASE]
724 str r0, [r5, #CLK_RESET_PLLX_BASE]
728 pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
737 str r0, [r5, #CLK_RESET_SCLK_BURST]
785 * r5 = TEGRA_CLK_RESET_BASE