Lines Matching refs:CPU
37 #define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */
179 * Powergates the current CPU.
183 /* Powergate this CPU */
192 * Puts the current CPU in wait-for-event mode on the flow controller
205 reteq lr @ Must never be called for CPU 0
210 add r1, r1, r12 @ virtual CSR address for this CPU
212 add r2, r2, r12 @ virtual HALT_EVENTS address for this CPU
215 * Clear this CPU's "event" and "interrupt" flags and power gate
229 /* Halt this CPU. */
260 wfeeq @ CPU should be power gated here
293 * CPU power-gating process, to avoid loading from SDRAM which
319 * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU.
328 /* Powergate this CPU. */
338 * Switches the CPU to enter sleep.
356 * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLX,
366 * The CPU and system bus are running at 32KHz and executing from
420 * CPUFreq driver could select other PLL for CPU. PLLX will be
658 * In LP0 and LP1 all PLLs will be turned off. Switching the CPU and System CLK
733 * Enable burst on CPU IRQ; bit 24=1
773 wfine /* CPU should be power gated here */