arm/mach-sunxi/mc_smp.c

87 static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
90 	int cpu = cluster * SUNXI_CPUS_PER_CLUSTER + core;
102 		 * would be mid way in a core or cluster power sequence.
104 		pr_err("%s: Couldn't get CPU cluster %u core %u device node\n",
105 		       __func__, cluster, core);
115 static int sunxi_cpu_power_switch_set(unsigned int cpu, unsigned int cluster,
121 	reg = readl(prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
124 			pr_debug("power clamp for cluster %u cpu %u already open\n",
125 				 cluster, cpu);
129 		writel(0xff, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
131 		writel(0xfe, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
133 		writel(0xf8, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
135 		writel(0xf0, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
137 		writel(0x00, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
140 		writel(0xff, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
158 static int sunxi_cpu_powerup(unsigned int cpu, unsigned int cluster)
162 	pr_debug("%s: cluster %u cpu %u\n", __func__, cluster, cpu);
163 	if (cpu >= SUNXI_CPUS_PER_CLUSTER || cluster >= SUNXI_NR_CLUSTERS)
167 	if (cluster == 0 && cpu == 0)
171 	reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
173 	writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
178 			     R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
181 		       R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
186 	if (!sunxi_core_is_cortex_a15(cpu, cluster)) {
187 		reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
189 		writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
193 	reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
200 	if (!sunxi_core_is_cortex_a15(cpu, cluster))
203 	writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
206 	sunxi_cpu_power_switch_set(cpu, cluster, true);
215 	reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
217 	writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
227 	reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
229 	writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
233 			     R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
236 		       R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
241 	reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
244 	if (!sunxi_core_is_cortex_a15(cpu, cluster))
248 	writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
253 static int sunxi_cluster_powerup(unsigned int cluster)
257 	pr_debug("%s: cluster %u\n", __func__, cluster);
258 	if (cluster >= SUNXI_NR_CLUSTERS)
261 	/* For A83T, assert cluster cores resets */
263 		reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
265 		writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
270 	reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
272 	writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
274 	/* assert cluster processor power-on resets */
275 	reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
277 	writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
279 	/* assert cluster cores resets */
282 			     R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
285 		       R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
289 	/* assert cluster resets */
290 	reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
300 	if (!sunxi_core_is_cortex_a15(0, cluster))
303 	writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
306 	reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
307 	if (sunxi_core_is_cortex_a15(0, cluster)) {
315 	writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
317 	/* clear cluster power gate */
318 	reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
323 	writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
326 	/* de-assert cluster resets */
327 	reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
331 	writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
334 	reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
336 	writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
343  * enable CCI-400 and proper cluster cache disable before power down.
359 	/* Flush all cache levels for this cluster. */
363 	 * Disable cluster-level coherency by masking
374 static bool sunxi_mc_smp_cluster_is_down(unsigned int cluster)
379 		if (sunxi_mc_smp_cpu_table[cluster][i])
393 	unsigned int mpidr, cpu, cluster;
397 	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
401 	if (cluster >= SUNXI_NR_CLUSTERS || cpu >= SUNXI_CPUS_PER_CLUSTER)
406 	if (sunxi_mc_smp_cpu_table[cluster][cpu])
409 	if (sunxi_mc_smp_cluster_is_down(cluster)) {
411 		sunxi_cluster_powerup(cluster);
418 	sunxi_cpu_powerup(cpu, cluster);
421 	sunxi_mc_smp_cpu_table[cluster][cpu]++;
430 	unsigned int cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
433 	pr_debug("%s: cluster %u\n", __func__, cluster);
438 	reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
440 	writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
445 	unsigned int mpidr, cpu, cluster;
450 	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
451 	pr_debug("%s: cluster %u cpu %u\n", __func__, cluster, cpu);
454 	sunxi_mc_smp_cpu_table[cluster][cpu]--;
455 	if (sunxi_mc_smp_cpu_table[cluster][cpu] == 1) {
461 	} else if (sunxi_mc_smp_cpu_table[cluster][cpu] > 1) {
463 		       cluster, cpu);
467 	last_man = sunxi_mc_smp_cluster_is_down(cluster);
480 static int sunxi_cpu_powerdown(unsigned int cpu, unsigned int cluster)
485 	pr_debug("%s: cluster %u cpu %u\n", __func__, cluster, cpu);
486 	if (cpu >= SUNXI_CPUS_PER_CLUSTER || cluster >= SUNXI_NR_CLUSTERS)
493 	reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
495 	writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
499 	sunxi_cpu_power_switch_set(cpu, cluster, false);
504 static int sunxi_cluster_powerdown(unsigned int cluster)
508 	pr_debug("%s: cluster %u\n", __func__, cluster);
509 	if (cluster >= SUNXI_NR_CLUSTERS)
512 	/* assert cluster resets or system will hang */
513 	pr_debug("%s: assert cluster reset\n", __func__);
514 	reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
518 	writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
520 	/* gate cluster power */
521 	pr_debug("%s: gate cluster power\n", __func__);
522 	reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
527 	writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
535 	unsigned int mpidr, cpu, cluster;
542 	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
545 	if (WARN_ON(cluster >= SUNXI_NR_CLUSTERS ||
564 		if (sunxi_mc_smp_cpu_table[cluster][cpu])
567 		reg = readl(cpucfg_base + CPUCFG_CX_STATUS(cluster));
578 	sunxi_cpu_powerdown(cpu, cluster);
580 	if (!sunxi_mc_smp_cluster_is_down(cluster))
583 	/* wait for cluster L2 WFI */
584 	ret = readl_poll_timeout(cpucfg_base + CPUCFG_CX_STATUS(cluster), reg,
589 		 * Ignore timeout on the cluster. Leaving the cluster on
598 	/* Power down cluster */
599 	sunxi_cluster_powerdown(cluster);
603 	pr_debug("%s: cluster %u cpu %u powerdown: %d\n",
604 		 __func__, cluster, cpu, ret);
630 	unsigned int mpidr, cpu, cluster;
634 	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
636 	if (cluster >= SUNXI_NR_CLUSTERS || cpu >= SUNXI_CPUS_PER_CLUSTER) {
640 	sunxi_mc_smp_cpu_table[cluster][cpu] = 1;
647  * We need the trampoline code to enable CCI-400 on the first cluster
868 	/* Configure CCI-400 for boot cluster */
871 		pr_err("%s: failed to configure boot cluster: %d\n",
886 	/* Actually enable multi cluster SMP */
889 	pr_info("sunxi multi cluster SMP support installed\n");