include/mach/SA-1100.h

137 #define UDCAR_ADD	Fld (7, 0)	/* function ADDress                */
139 #define UDCOMP_OUTMAXP	Fld (8, 0)	/* OUTput MAXimum Packet size - 1  */
145 #define UDCIMP_INMAXP	Fld (8, 0)	/* INput MAXimum Packet size - 1   */
177 #define UDCD0_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs     */
179 #define UDCWC_WC	Fld (4, 0)	/* Write Count                     */
181 #define UDCDR_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs     */
337 #define UTCR1_BRD	Fld (4, 0)	/* Baud Rate Divisor/16 - 1 [11:8] */
338 #define UTCR2_BRD	Fld (8, 0)	/* Baud Rate Divisor/16 - 1  [7:0] */
378 #define UTDR_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs     */
474 #define SDCR2_AMV	Fld (8, 0)	/* Address Match Value             */
476 #define SDCR3_BRD	Fld (4, 0)	/* Baud Rate Divisor/16 - 1 [11:8] */
477 #define SDCR4_BRD	Fld (8, 0)	/* Baud Rate Divisor/16 - 1  [7:0] */
497 #define SDDR_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs     */
565 #define HSCR1_AMV	Fld (8, 0)	/* Address Match Value             */
567 #define HSDR_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs     */
637 #define MCCR0_ASD	Fld (7, 0)	/* Audio Sampling rate Divisor/32  */
650 #define MCCR0_TSD	Fld (7, 8)	/* Telecom Sampling rate           */
680 #define MCCR0_ECP	Fld (2, 24)	/* External Clock Prescaler - 1    */
684 #define MCDR0_DATA	Fld (12, 4)	/* receive/transmit audio DATA     */
687 #define MCDR1_DATA	Fld (14, 2)	/* receive/transmit telecom DATA   */
692 #define MCDR2_DATA	Fld (16, 0)	/*  reg. DATA                      */
696 #define MCDR2_ADD	Fld (4, 17)	/*  reg. ADDress                   */
758 #define SSCR0_DSS	Fld (4, 0)	/* Data Size - 1 Select [3..15]    */
761 #define SSCR0_FRF	Fld (2, 4)	/* FRame Format                    */
771 #define SSCR0_SCR	Fld (8, 8)	/* Serial Clock Rate divisor/2 - 1 */
800 #define SSDR_DATA	Fld (16, 0)	/* receive/transmit DATA FIFOs     */
945 #define PPCR_CCF	Fld (5, 0)	/* CPU core Clock (CCLK) Freq.     */
1054 #define TUCR_CTB	Fld (3, 20)	/* Clock Test Bits                 */
1059 #define TUCR_TSEL	Fld (3, 29)	/* clock Test SELect on GPIO [27]  */
1380 #define MDCNFG_DRAC	Fld (2, 4)	/* DRAM Row Address Count - 9      */
1385 #define MDCNFG_TRP	Fld (4, 7)	/* Time RAS Pre-charge - 1 [Tmem]  */
1390 #define MDCNFG_TRASR	Fld (4, 11)	/* Time RAS Refresh - 1 [Tmem]     */
1395 #define MDCNFG_TDL	Fld (2, 15)	/* Time Data Latch [Tcpu]          */
1398 #define MDCNFG_DRI	Fld (15, 17)	/* min. DRAM Refresh Interval/4    */
1409 #define MDCNFG_SA1110_DRAC0	Fld(3, 4)	/* DRAM row addr bit count   */
1412 #define MDCNFG_SA1110_TRP0	Fld(3, 8)	/* RAS precharge 0/1         */
1413 #define MDCNFG_SA1110_TDL0	Fld(2, 12)	/* Data input latch after CAS*/
1415 #define MDCNFG_SA1110_TWR0	Fld(2, 14)	/* SDRAM write recovery 0/1  */
1420 #define MDCNFG_SA1110_DRAC2	Fld(3, 20)	/* DRAM row addr bit count   */
1423 #define MDCNFG_SA1110_TRP2	Fld(3, 24)	/* RAS precharge 0/1         */
1424 #define MDCNFG_SA1110_TDL2	Fld(2, 28)	/* Data input latch after CAS*/
1426 #define MDCNFG_SA1110_TWR2	Fld(2, 30)	/* SDRAM write recovery 0/1  */
1448                 	Fld (16, ((Nb) Modulo 2)*16)
1454 #define MSC_RT  	Fld (2, 0)	/* ROM/static memory Type          */
1466 #define MSC_RDF 	Fld (5, 3)	/* ROM/static memory read Delay    */
1478 #define MSC_RDN 	Fld (5, 8)	/* ROM/static memory read Delay    */
1490 #define MSC_RRR 	Fld (3, 13)	/* ROM/static memory RecoveRy      */
1516                 	Fld (15, (Nb)*16)
1520 #define MECR_BSIO	Fld (5, 0)	/* BCLK Select I/O - 1 [Tmem]      */
1525 #define MECR_BSA	Fld (5, 5)	/* BCLK Select Attribute - 1       */
1531 #define MECR_BSM	Fld (5, 10)	/* BCLK Select Memory - 1 [Tmem]   */
1543 #define MDREFR_TRASR		Fld (4, 0)
1544 #define MDREFR_DRI		Fld (12, 4)
1628 #define LCD_PGrey	Fld (4, 0)	/* LCD Palette entry Grey value    */
1629 #define LCD_PBlue	Fld (4, 0)	/* LCD Palette entry Blue value    */
1630 #define LCD_PGreen	Fld (4, 4)	/* LCD Palette entry Green value   */
1631 #define LCD_PRed	Fld (4, 8)	/* LCD Palette entry Red value     */
1632 #define LCD_PBS 	Fld (2, 12)	/* LCD Pixel Bit Size              */
1685 #define LCCR0_PDD	Fld (8, 12)	/* Palette DMA request Delay       */
1712 #define LCCR1_PPL	Fld (6, 4)	/* Pixels Per Line/16 - 1          */
1715 #define LCCR1_HSW	Fld (6, 10)	/* Horizontal Synchronization      */
1720 #define LCCR1_ELW	Fld (8, 16)	/* End-of-Line pixel clock Wait    */
1725 #define LCCR1_BLW	Fld (8, 24)	/* Beginning-of-Line pixel clock   */
1731 #define LCCR2_LPP	Fld (10, 0)	/* Line Per Panel - 1              */
1734 #define LCCR2_VSW	Fld (6, 10)	/* Vertical Synchronization pulse  */
1739 #define LCCR2_EFW	Fld (8, 16)	/* End-of-Frame line clock Wait    */
1744 #define LCCR2_BFW	Fld (8, 24)	/* Beginning-of-Frame line clock   */
1750 #define LCCR3_PCD	Fld (8, 0)	/* Pixel Clock Divisor/2 - 2       */
1762 #define LCCR3_ACB	Fld (8, 8)	/* AC Bias clock half period - 1   */
1772 #define LCCR3_API	Fld (4, 16)	/* AC bias Pin transitions per     */