arm/mach-omap2/sram242x.S

5  * Omap2 specific functions that need to be run in internal SRAM
11  * Richard Woodruff notes that any changes to this code must be carefully
12  * audited and tested to ensure that they don't cause a TLB miss while
14  * since it will cause the ARM MMU to attempt to walk the page tables.
39 	str	r3, [r2]		@ go to L1-freq operation
49 	addeq	r11, r11, #0x8		@ if cs1 base, move to DLLB
50 	mvn	r9, #0x4		@ mask to get clear bit2
54 	str	r10, [r11]		@ commit to DLLA_CTRL
55 	bl	i_dll_wait		@ wait for dll to lock
62 	mov r9, #0x0			@ shift back to L0-voltage
67 	str	r3, [r2]		@ go to L0-freq operation
70 	sub	r11, r11, #0x4		@ move from status to ctrl
72 	subeq	r11, r11, #0x8		@ possibly back to DLLA
76 	add	r11, r11, #0x8		@ move to DLLB_CTRL addr
93 	 * shift up or down voltage, use R9 as input to tell level.
94 	 * wait for it to finish, use 32k sync counter, 1tick=31uS.
100 	and	r5, r5, r6		@ apply mask to clear bits
105 	str	r5, [r4]		@ Force transition to L1
114 	ret	lr			@ back to caller.
145 	cmp	r0, #0x1		@ going to half speed?
150 	cmp	r0, #0x1		@ going to half speed (post branch link)
151 	moveq	r5, r5, lsr #1		@ divide by 2 if to half
152 	movne	r5, r5, lsl #1		@ mult by 2 if to full
172 	cmp	r2, #0x1		@ (SDR or DDR) do we need to adjust DLL
175 	/* With DDR, we need to take care of the DLL for the frequency change */
178 	add	r2, r2, #0x8		@ addr to SDRC_DLLB_CTRL
179 	str	r1, [r2]		@ commit to SDRC_DLLB_CTRL
188      * shift up or down voltage, use R9 as input to tell level.
189      *	wait for it to finish, use 32k sync counter, 1tick=31uS.
195 	and	r8, r8, r7		@ apply mask to clear bits
200 	str	r8, [r10]		@ Force transition to L1
209 	ret	lr			@ back to caller
232 	stmfd	sp!, {r0-r12, lr}	@ regs to stack
243 	str	r7, [r8]		@ go to fast relock
289 	mvn	r9, #0x4		@ mask to get clear bit2
292 	str	r10, [r11]		@ commit to DLLA_CTRL
293 	add	r11, r11, #0x8		@ move to dllb