Lines Matching refs:name
19 * The overly-specific dep_bit names are due to a bit name collision
223 .name = "mpu_clkdm",
224 .pwrdm = { .name = "mpu_pwrdm" },
232 .name = "mpu_clkdm",
233 .pwrdm = { .name = "mpu_pwrdm" },
241 .name = "neon_clkdm",
242 .pwrdm = { .name = "neon_pwrdm" },
249 .name = "iva2_clkdm",
250 .pwrdm = { .name = "iva2_pwrdm" },
258 .name = "gfx_clkdm",
259 .pwrdm = { .name = "gfx_pwrdm" },
267 .name = "sgx_clkdm",
268 .pwrdm = { .name = "sgx_pwrdm" },
276 .name = "sgx_clkdm",
277 .pwrdm = { .name = "sgx_pwrdm" },
292 .name = "d2d_clkdm",
293 .pwrdm = { .name = "core_pwrdm" },
304 .name = "core_l3_clkdm",
305 .pwrdm = { .name = "core_pwrdm" },
317 .name = "core_l4_clkdm",
318 .pwrdm = { .name = "core_pwrdm" },
324 /* Another case of bit name collisions between several registers: EN_DSS */
326 .name = "dss_clkdm",
327 .pwrdm = { .name = "dss_pwrdm" },
336 .name = "dss_clkdm",
337 .pwrdm = { .name = "dss_pwrdm" },
346 .name = "cam_clkdm",
347 .pwrdm = { .name = "cam_pwrdm" },
355 .name = "usbhost_clkdm",
356 .pwrdm = { .name = "usbhost_pwrdm" },
364 .name = "usbhost_clkdm",
365 .pwrdm = { .name = "core_pwrdm" },
373 .name = "per_clkdm",
374 .pwrdm = { .name = "per_pwrdm" },
383 .name = "per_clkdm",
384 .pwrdm = { .name = "per_pwrdm" },
393 .name = "emu_clkdm",
394 .pwrdm = { .name = "emu_pwrdm" },
401 .name = "dpll1_clkdm",
402 .pwrdm = { .name = "dpll1_pwrdm" },
406 .name = "dpll2_clkdm",
407 .pwrdm = { .name = "dpll2_pwrdm" },
411 .name = "dpll3_clkdm",
412 .pwrdm = { .name = "dpll3_pwrdm" },
416 .name = "dpll4_clkdm",
417 .pwrdm = { .name = "dpll4_pwrdm" },
421 .name = "dpll5_clkdm",
422 .pwrdm = { .name = "dpll5_pwrdm" },
431 .clkdm = { .name = "mpu_clkdm" },
434 .clkdm = { .name = "iva2_clkdm" },
437 .clkdm = { .name = NULL },
443 .clkdm = { .name = "mpu_clkdm" },
446 .clkdm = { .name = NULL },