arm/mach-meson/platsmp.c

159 	int ret;
170 	ret = reset_control_assert(rstc);
171 	if (ret) {
177 	ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
179 	if (ret < 0) {
187 	ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
189 	if (ret < 0) {
195 	ret = reset_control_deassert(rstc);
196 	if (ret) {
201 	ret = meson_smp_finalize_secondary_boot(cpu);
202 	if (ret)
215 	int ret;
227 	ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0,
229 	if (ret < 0) {
237 	ret = reset_control_assert(rstc);
238 	if (ret) {
244 	ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_MEM_PD0,
246 	if (ret < 0) {
252 	ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
254 	if (ret < 0) {
261 	ret = regmap_read_poll_timeout(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1, val,
264 	if (ret) {
270 	ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
272 	if (ret < 0) {
278 	ret = reset_control_deassert(rstc);
279 	if (ret) {
284 	ret = meson_smp_finalize_secondary_boot(cpu);
285 	if (ret)
312 	int ret, power_mode;
334 	ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
336 	if (ret < 0) {
338 		return ret;
344 	ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
346 	if (ret < 0) {
348 		return ret;
356 	int ret, power_mode, count = 5000;
376 	ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0,
378 	if (ret < 0) {
380 		return ret;
384 	ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
386 	if (ret < 0) {
388 		return ret;
394 	ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
396 	if (ret < 0) {
398 		return ret;
402 	ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_MEM_PD0,
404 	if (ret < 0) {
406 		return ret;