Lines Matching defs:rate
45 * PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS
47 static unsigned long calc_pll_rate(unsigned long long rate, u32 config_word)
51 rate *= ((config_word >> 11) & 0x1f) + 1; /* X1FBD */
52 rate *= ((config_word >> 5) & 0x3f) + 1; /* X2FBD */
53 do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */
55 rate >>= 1;
57 return (unsigned long)rate;
202 static bool is_best(unsigned long rate, unsigned long now,
205 return abs(rate - now) < abs(rate - best);
211 unsigned long rate = req->rate;
236 __div = mclk_rate / (rate * __pdiv);
241 if (is_best(rate, actual_rate, best_rate)) {
254 req->rate = best_rate;
263 unsigned long rate = 0;
269 rate = (parent_rate * 2) / ((__pdiv + 3) * __div);
271 return rate;
274 static int ep93xx_ddiv_set_rate(struct clk_hw *hw, unsigned long rate,
286 __div = mclk_rate / (rate * __pdiv);
291 if (is_best(rate, actual_rate, best_rate)) {
306 /* Set the new pdiv and div bits for the new clock rate */
368 static long ep93xx_div_round_rate(struct clk_hw *hw, unsigned long rate,
378 if ((rate * psc->div[i]) == *parent_rate)
383 if (is_best(rate, now, best))
393 static int ep93xx_div_set_rate(struct clk_hw *hw, unsigned long rate,
401 if (rate == parent_rate / psc->div[i]) {
555 /* Determine the bootloader configured pll1 rate */
581 /* Determine the bootloader configured pll2 rate */
626 * EP93xx SSP clock rate was doubled in version E2. For more information