arm/mach-davinci/sleep.S

43 	ldr 	ip, CACHE_FLUSH
44 	blx	ip
53 	ldr	ip, [r0, #DDR2_SDRCR_OFFSET]
54 	bic	ip, ip, #DDR2_SRPD_BIT
55 	orr	ip, ip, #DDR2_LPMODEN_BIT
56 	str	ip, [r0, #DDR2_SDRCR_OFFSET]
58 	ldr	ip, [r0, #DDR2_SDRCR_OFFSET]
59 	orr	ip, ip, #DDR2_MCLKSTOPEN_BIT
60 	str	ip, [r0, #DDR2_SDRCR_OFFSET]
62        mov	ip, #PHYRDY_CYCLES
63 1:     subs	ip, ip, #0x1
73 	ldr	ip, [r3, #PLLDIV1]
74 	bic	ip, ip, #PLLDIV_EN
75 	str	ip, [r3, #PLLDIV1]
78 	ldr	ip, [r3, #PLLCTL]
79 	bic	ip, ip, #PLLCTL_PLLENSRC
80 	bic	ip, ip, #PLLCTL_PLLEN
81 	str	ip, [r3, #PLLCTL]
84        mov	ip, #PLL_BYPASS_CYCLES
85 2:     subs	ip, ip, #0x1
89 	ldr	ip, [r3, #PLLCTL]
90 	orr	ip, ip, #PLLCTL_PLLPWRDN
91 	str	ip, [r3, #PLLCTL]
94 	ldr	ip, [r4]
95 	orr	ip, ip, #DEEPSLEEP_SLEEPENABLE_BIT
97 	str	ip, [r4]
102 	ldr	ip, [r4]
103 	bic	ip, ip, #DEEPSLEEP_SLEEPENABLE_BIT
104 	str	ip, [r4]
109 	ldr	ip, [r3, #PLLCTL]
110 	bic	ip, ip, #PLLCTL_PLLRST
111 	str	ip, [r3, #PLLCTL]
114 	ldr	ip, [r3, #PLLCTL]
115 	bic	ip, ip, #PLLCTL_PLLPWRDN
116 	str	ip, [r3, #PLLCTL]
118        mov	ip, #PLL_RESET_CYCLES
119 3:     subs	ip, ip, #0x1
123 	ldr	ip, [r3, #PLLCTL]
124 	orr	ip, ip, #PLLCTL_PLLRST
125 	str	ip, [r3, #PLLCTL]
128        mov	ip, #PLL_LOCK_CYCLES
129 4:     subs	ip, ip, #0x1
133 	ldr	ip, [r3, #PLLCTL]
134 	bic	ip, ip, #PLLCTL_PLLENSRC
135 	orr	ip, ip, #PLLCTL_PLLEN
136 	str	ip, [r3, #PLLCTL]
140 	ldr	ip, [r3, #PLLDIV1]
141 	orr	ip, ip, #PLLDIV_EN
142 	str	ip, [r3, #PLLDIV1]
154 	ldr	ip, [r0, #DDR2_SDRCR_OFFSET]
155 	bic	ip, ip, #DDR2_MCLKSTOPEN_BIT
156 	str	ip, [r0, #DDR2_SDRCR_OFFSET]
158 	ldr	ip, [r0, #DDR2_SDRCR_OFFSET]
159 	bic	ip, ip, #DDR2_LPMODEN_BIT
160 	str	ip, [r0, #DDR2_SDRCR_OFFSET]
178 	ldr	ip, [r1, r6]
179 	bic	ip, ip, #MDSTAT_STATE_MASK
180 	orr	ip, ip, r0
181 	str	ip, [r1, r6]
184 	ldr	ip, [r1, #PTCMD]
185 	orr	ip, ip, #0x1
186 	str	ip, [r1, #PTCMD]
190 	ldr	ip, [r1, #PTSTAT]
191 	and	ip, ip, #0x1
192 	cmp 	ip, #0x0
199 	ldr	ip, [r1, r6]
200 	and	ip, ip, #MDSTAT_STATE_MASK
201 	cmp	ip, r0