arm/kernel/perf_event_v6.c

3  * ARMv6 Performance counter handling code.
7  * ARMv6 has 2 configurable performance counters and a single cycle counter.
16  * the event bus. The procedure for disabling a configurable counter is:
17  *	- change the counter to count the ETMEXTOUT[0] signal (0x20). This
18  *	  effectively stops the counter from counting.
19  *	- disable the counter's interrupt generation (each counter has it's
21  * Once stopped, the counter value can be written as 0 to reset.
23  * To enable a counter:
24  *	- enable the counter's interrupt generation.
27  * Note: the dedicated cycle counter only counts cycles and can't be
29  * cycle counter, we have to just disable the interrupt reporting and start
30  * ignoring that counter. When re-enabling, we have to reset the value and
107 	 * can use a raw counter.
157 				  enum armv6_counters counter)
161 	if (ARMV6_CYCLE_COUNTER == counter)
163 	else if (ARMV6_COUNTER0 == counter)
165 	else if (ARMV6_COUNTER1 == counter)
168 		WARN_ONCE(1, "invalid counter number (%d)\n", counter);
176 	int counter = hwc->idx;
179 	if (ARMV6_CYCLE_COUNTER == counter)
181 	else if (ARMV6_COUNTER0 == counter)
183 	else if (ARMV6_COUNTER1 == counter)
186 		WARN_ONCE(1, "invalid counter number (%d)\n", counter);
194 	int counter = hwc->idx;
196 	if (ARMV6_CYCLE_COUNTER == counter)
198 	else if (ARMV6_COUNTER0 == counter)
200 	else if (ARMV6_COUNTER1 == counter)
203 		WARN_ONCE(1, "invalid counter number (%d)\n", counter);
224 		WARN_ONCE(1, "invalid counter number (%d)\n", idx);
229 	 * Mask out the current event and set the counter to count the event
269 		 * each counter has overflowed before we process it.
319 	/* Always place a cycle counter into the cycle counter. */
327 		 * For anything other than a cycle counter, try and use
363 		WARN_ONCE(1, "invalid counter number (%d)\n", idx);
368 	 * Mask out the current event and set the counter to count the number