Lines Matching refs:r9
50 * - MMU_SCRATCH0 Reg used for freeing up r9 in Level 1 ISR
169 ld r9, [sp, PT_status32] ; get statu32_l2 (saved in pt_regs)
170 bbit0 r9, STATUS_A1_BIT, 1f ; L1 not active when L2 IRQ, so normal
174 ld r9, [r10, THREAD_INFO_PREEMPT_COUNT]
175 add r9, r9, 1
176 st r9, [r10, THREAD_INFO_PREEMPT_COUNT]
339 ld r9, [sp, PT_event] ; Ensure this is L2 intr context
340 brne r9, event_IRQ2, 149f
349 ld r9, [sp, PT_status32] ; get statu32_l2 (saved in pt_regs)
350 bbit0 r9, STATUS_A1_BIT, 149f ; L1 not active when L2 IRQ, so normal
354 ld r9, [r10, THREAD_INFO_PREEMPT_COUNT]
359 cmp r9, 0
364 sub r9, r9, 1
365 st r9, [r10, THREAD_INFO_PREEMPT_COUNT]