arc/kernel/disasm.c

19  * findings in *state
21 void __kprobes disasm_instr(unsigned long addr, struct disasm_state *state,
32 	memset(state, 0, sizeof(struct disasm_state));
48 	state->major_opcode = (word1 >> 11) & 0x1F;
51 	if (state->major_opcode < 0x0B) {
54 		state->instr_len = 4;
56 		state->words[0] = (word1 << 16) | word0;
58 		state->instr_len = 2;
59 		state->words[0] = word1;
63 	word1 = *((uint16_t *)(addr + state->instr_len));
64 	word0 = *((uint16_t *)(addr + state->instr_len + 2));
65 	state->words[1] = (word1 << 16) | word0;
67 	switch (state->major_opcode) {
69 		state->is_branch = 1;
72 		fieldA = (IS_BIT(state->words[0], 16)) ?
73 			FIELD_s25(state->words[0]) :
74 			FIELD_s21(state->words[0]);
76 		state->delay_slot = IS_BIT(state->words[0], 5);
77 		state->target = fieldA + (addr & ~0x3);
78 		state->flow = direct_jump;
82 		if (IS_BIT(state->words[0], 16)) {
85 			fieldA = (IS_BIT(state->words[0], 17)) ?
86 				(FIELD_s25(state->words[0]) & ~0x3) :
87 				FIELD_s21(state->words[0]);
89 			state->flow = direct_call;
92 			fieldA = FIELD_s9(state->words[0]) & ~0x3;
93 			state->flow = direct_jump;
96 		state->delay_slot = IS_BIT(state->words[0], 5);
97 		state->target = fieldA + (addr & ~0x3);
98 		state->is_branch = 1;
102 		state->write = 0;
103 		state->di = BITS(state->words[0], 11, 11);
104 		if (state->di)
106 		state->x = BITS(state->words[0], 6, 6);
107 		state->zz = BITS(state->words[0], 7, 8);
108 		state->aa = BITS(state->words[0], 9, 10);
109 		state->wb_reg = FIELD_B(state->words[0]);
110 		if (state->wb_reg == REG_LIMM) {
111 			state->instr_len += 4;
112 			state->aa = 0;
113 			state->src1 = state->words[1];
115 			state->src1 = get_reg(state->wb_reg, regs, cregs);
117 		state->src2 = FIELD_s9(state->words[0]);
118 		state->dest = FIELD_A(state->words[0]);
119 		state->pref = (state->dest == REG_LIMM);
123 		state->write = 1;
124 		state->di = BITS(state->words[0], 5, 5);
125 		if (state->di)
127 		state->aa = BITS(state->words[0], 3, 4);
128 		state->zz = BITS(state->words[0], 1, 2);
129 		state->src1 = FIELD_C(state->words[0]);
130 		if (state->src1 == REG_LIMM) {
131 			state->instr_len += 4;
132 			state->src1 = state->words[1];
134 			state->src1 = get_reg(state->src1, regs, cregs);
136 		state->wb_reg = FIELD_B(state->words[0]);
137 		if (state->wb_reg == REG_LIMM) {
138 			state->aa = 0;
139 			state->instr_len += 4;
140 			state->src2 = state->words[1];
142 			state->src2 = get_reg(state->wb_reg, regs, cregs);
144 		state->src3 = FIELD_s9(state->words[0]);
148 		subopcode = MINOR_OPCODE(state->words[0]);
157 				state->delay_slot = 1;
163 			op_format = BITS(state->words[0], 22, 23);
165 				(!IS_BIT(state->words[0], 5)))) {
166 				fieldC = FIELD_C(state->words[0]);
169 					fieldC = state->words[1];
170 					state->instr_len += 4;
175 				&& (IS_BIT(state->words[0], 5)))) {
176 				fieldC = FIELD_C(state->words[0]);
179 				fieldC = FIELD_s12(state->words[0]);
183 				state->target = fieldC;
184 				state->flow = is_linked ?
187 				state->target = get_reg(fieldC, regs, cregs);
188 				state->flow = is_linked ?
191 			state->is_branch = 1;
195 			if (BITS(state->words[0], 22, 23) == 3) {
197 				fieldC = FIELD_C(state->words[0]);
201 				state->is_branch = 1;
202 				state->flow = direct_jump;
203 				state->target = fieldC;
210 			state->di = BITS(state->words[0], 15, 15);
211 			if (state->di)
213 			state->x = BITS(state->words[0], 16, 16);
214 			state->zz = BITS(state->words[0], 17, 18);
215 			state->aa = BITS(state->words[0], 22, 23);
216 			state->wb_reg = FIELD_B(state->words[0]);
217 			if (state->wb_reg == REG_LIMM) {
218 				state->instr_len += 4;
219 				state->src1 = state->words[1];
221 				state->src1 = get_reg(state->wb_reg, regs,
224 			state->src2 = FIELD_C(state->words[0]);
225 			if (state->src2 == REG_LIMM) {
226 				state->instr_len += 4;
227 				state->src2 = state->words[1];
229 				state->src2 = get_reg(state->src2, regs,
232 			state->dest = FIELD_A(state->words[0]);
233 			if (state->dest == REG_LIMM)
234 				state->pref = 1;
240 			switch (BITS(state->words[0], 22, 23)) {
242 				if (FIELD_C(state->words[0]) == REG_LIMM)
243 					state->instr_len += 4;
250 				if ((!IS_BIT(state->words[0], 5)) &&
251 				    (FIELD_C(state->words[0]) == REG_LIMM))
252 					state->instr_len += 4;
261 			switch (BITS(state->words[0], 22, 23)) {
263 				if ((FIELD_B(state->words[0]) == REG_LIMM) ||
264 				    (FIELD_C(state->words[0]) == REG_LIMM))
265 					state->instr_len += 4;
272 				if ((!IS_BIT(state->words[0], 5)) &&
273 				   ((FIELD_B(state->words[0]) == REG_LIMM) ||
274 				    (FIELD_C(state->words[0]) == REG_LIMM)))
275 					state->instr_len += 4;
284 		state->zz = BITS(state->words[0], 3, 4);
285 		state->src1 = get_reg(FIELD_S_B(state->words[0]), regs, cregs);
286 		state->src2 = get_reg(FIELD_S_C(state->words[0]), regs, cregs);
287 		state->dest = FIELD_S_A(state->words[0]);
292 		if ((BITS(state->words[0], 3, 4) < 3) &&
293 		    (FIELD_S_H(state->words[0]) == REG_LIMM))
294 			state->instr_len += 4;
298 		subopcode = BITS(state->words[0], 5, 7);
304 			state->target = get_reg(FIELD_S_B(state->words[0]),
306 			state->delay_slot = subopcode & 1;
307 			state->flow = (subopcode >= 2) ?
311 			switch (BITS(state->words[0], 8, 10)) {
316 				state->delay_slot = (subopcode == 7);
317 				state->flow = indirect_jump;
318 				state->target = get_reg(31, regs, cregs);
328 		state->src1 = get_reg(FIELD_S_B(state->words[0]), regs, cregs);
329 		state->src2 = FIELD_S_u7(state->words[0]);
330 		state->dest = FIELD_S_C(state->words[0]);
337 		state->zz = 1;
341 		state->x = 1;
345 		state->zz = 2;
346 		state->src1 = get_reg(FIELD_S_B(state->words[0]), regs, cregs);
347 		state->src2 = FIELD_S_u6(state->words[0]);
348 		state->dest = FIELD_S_C(state->words[0]);
352 		state->write = 1;
353 		state->src1 = get_reg(FIELD_S_C(state->words[0]), regs, cregs);
354 		state->src2 = get_reg(FIELD_S_B(state->words[0]), regs, cregs);
355 		state->src3 = FIELD_S_u7(state->words[0]);
359 		state->write = 1;
360 		state->zz = 2;
361 		state->src1 = get_reg(FIELD_S_C(state->words[0]), regs, cregs);
362 		state->src2 = get_reg(FIELD_S_B(state->words[0]), regs, cregs);
363 		state->src3 = FIELD_S_u6(state->words[0]);
370 		state->write = BITS(state->words[0], 6, 6);
371 		state->zz = BITS(state->words[0], 5, 5);
372 		if (state->zz)
374 		if (!state->write) {
375 			state->src1 = get_reg(28, regs, cregs);
376 			state->src2 = FIELD_S_u7(state->words[0]);
377 			state->dest = FIELD_S_B(state->words[0]);
379 			state->src1 = get_reg(FIELD_S_B(state->words[0]), regs,
381 			state->src2 = get_reg(28, regs, cregs);
382 			state->src3 = FIELD_S_u7(state->words[0]);
388 		state->zz = BITS(state->words[0], 9, 10);
389 		state->src1 = get_reg(26, regs, cregs);
390 		state->src2 = state->zz ? FIELD_S_s10(state->words[0]) :
391 			FIELD_S_s11(state->words[0]);
392 		state->dest = 0;
396 		state->src1 = regs->ret & ~3;
397 		state->src2 = FIELD_S_u10(state->words[0]);
398 		state->dest = FIELD_S_B(state->words[0]);
402 		state->target = FIELD_S_s8(state->words[0]) + (addr & ~0x03);
403 		state->flow = direct_jump;
404 		state->is_branch = 1;
408 		fieldA = (BITS(state->words[0], 9, 10) == 3) ?
409 			FIELD_S_s7(state->words[0]) :
410 			FIELD_S_s10(state->words[0]);
411 		state->target = fieldA + (addr & ~0x03);
412 		state->flow = direct_jump;
413 		state->is_branch = 1;
417 		state->target = FIELD_S_s13(state->words[0]) + (addr & ~0x03);
418 		state->flow = direct_call;
419 		state->is_branch = 1;
426 	if (bytes_not_copied <= (8 - state->instr_len))
429 fault:	state->fault = 1;