include/asm/core_irongate.h

35 typedef volatile __u32	igcsr32;
38 	igcsr32 dev_vendor;		/* 0x00 - device ID, vendor ID */
39 	igcsr32 stat_cmd;		/* 0x04 - status, command */
40 	igcsr32 class;			/* 0x08 - class code, rev ID */
41 	igcsr32 latency;		/* 0x0C - header type, PCI latency */
42 	igcsr32 bar0;			/* 0x10 - BAR0 - AGP */
43 	igcsr32 bar1;			/* 0x14 - BAR1 - GART */
44 	igcsr32 bar2;			/* 0x18 - Power Management reg block */
46 	igcsr32 rsrvd0[6];		/* 0x1C-0x33 reserved */
48 	igcsr32 capptr;			/* 0x34 - Capabilities pointer */
50 	igcsr32 rsrvd1[2];		/* 0x38-0x3F reserved */
52 	igcsr32 bacsr10;		/* 0x40 - base address chip selects */
53 	igcsr32 bacsr32;		/* 0x44 - base address chip selects */
54 	igcsr32 bacsr54_eccms761;	/* 0x48 - 751: base addr. chip selects
57 	igcsr32 rsrvd2[1];		/* 0x4C-0x4F reserved */
59 	igcsr32 drammap;		/* 0x50 - address mapping control */
60 	igcsr32 dramtm;			/* 0x54 - timing, driver strength */
61 	igcsr32 dramms;			/* 0x58 - DRAM mode/status */
63 	igcsr32 rsrvd3[1];		/* 0x5C-0x5F reserved */
65 	igcsr32 biu0;			/* 0x60 - bus interface unit */
66 	igcsr32 biusip;			/* 0x64 - Serial initialisation pkt */
68 	igcsr32 rsrvd4[2];		/* 0x68-0x6F reserved */
70 	igcsr32 mro;			/* 0x70 - memory request optimiser */
72 	igcsr32 rsrvd5[3];		/* 0x74-0x7F reserved */
74 	igcsr32 whami;			/* 0x80 - who am I */
75 	igcsr32 pciarb;			/* 0x84 - PCI arbitration control */
76 	igcsr32 pcicfg;			/* 0x88 - PCI config status */
78 	igcsr32 rsrvd6[4];		/* 0x8C-0x9B reserved */
80 	igcsr32 pci_mem;		/* 0x9C - PCI top of memory,
84 	igcsr32 agpcap;			/* 0xA0 - AGP Capability Identifier */
85 	igcsr32 agpstat;		/* 0xA4 - AGP status register */
86 	igcsr32 agpcmd;			/* 0xA8 - AGP control register */
87 	igcsr32 agpva;			/* 0xAC - AGP Virtual Address Space */
88 	igcsr32 agpmode;		/* 0xB0 - AGP/GART mode control */
94 	igcsr32 dev_vendor;		/* 0x00 - Device and Vendor IDs */
95 	igcsr32 stat_cmd;		/* 0x04 - Status and Command regs */
96 	igcsr32 class;			/* 0x08 - subclass, baseclass etc */
97 	igcsr32 htype;			/* 0x0C - header type (at 0x0E) */
98 	igcsr32 rsrvd0[2];		/* 0x10-0x17 reserved */
99 	igcsr32 busnos;			/* 0x18 - Primary, secondary bus nos */
100 	igcsr32 io_baselim_regs;	/* 0x1C - IO base, IO lim, AGP status */
101 	igcsr32	mem_baselim;		/* 0x20 - memory base, memory lim */
102 	igcsr32 pfmem_baselim;		/* 0x24 - prefetchable base, lim */
103 	igcsr32 rsrvd1[2];		/* 0x28-0x2F reserved */
104 	igcsr32 io_baselim;		/* 0x30 - IO base, IO limit */
105 	igcsr32 rsrvd2[2];		/* 0x34-0x3B - reserved */
106 	igcsr32 interrupt;		/* 0x3C - interrupt, PCI bridge ctrl */
110 extern igcsr32 *IronECC;