Lines Matching refs:x2
74 cmp x1, #0x2
79 mov x2, #(HCR_RW)
80 msr hcr_el2, x2
83 mrs x2, midr_el1
84 msr vpidr_el2, x2
87 mrs x2, mpidr_el1
88 msr vmpidr_el2, x2
91 ldr x2, .Lsctlr_res1
92 msr sctlr_el1, x2
95 mov x2, #CPTR_RES1
96 msr cptr_el2, x2
102 mrs x2, cnthctl_el2
103 orr x2, x2, #(CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN)
104 msr cnthctl_el2, x2
110 // adr x2, hyp_vectors
111 // msr vbar_el2, x2
113 mov x2, #(PSR_F | PSR_I | PSR_A | PSR_D | PSR_M_EL1h)
114 msr spsr_el2, x2
117 mrs x2, id_aa64pfr0_el1
119 ubfx x2, x2, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_BITS
121 cmp x2, #(ID_AA64PFR0_GIC_CPUIF_EN >> ID_AA64PFR0_GIC_SHIFT)
124 mrs x2, S3_4_C12_C9_5
125 orr x2, x2, #ICC_SRE_EL2_EN /* Enable access from insecure EL1 */
126 orr x2, x2, #ICC_SRE_EL2_SRE /* Enable system registers */
127 msr S3_4_C12_C9_5, x2