Lines Matching defs:timing
46 crtc_info_block* timing;
155 get_crtc_info_block(edid1_detailed_timing& timing)
161 // Copy timing structure to set the mode with
168 crtcInfo->horizontal_sync_start = timing.h_active + timing.h_sync_off;
170 + timing.h_sync_width;
171 crtcInfo->horizontal_total = timing.h_active + timing.h_blank;
172 crtcInfo->vertical_sync_start = timing.v_active + timing.v_sync_off;
174 + timing.v_sync_width;
175 crtcInfo->vertical_total = timing.v_active + timing.v_blank;
176 crtcInfo->pixel_clock = timing.pixel_clock * 10000L;
188 if (timing.sync == 3) {
191 if ((timing.misc & 1) == 0)
193 if ((timing.misc & 2) == 0)
196 if (timing.interlaced)
204 get_crtc_info_block(edid1_std_timing& timing)
216 // try detailed timing first
224 mode->timing
255 mode->timing = get_crtc_info_block(info.std_timing[best]);
520 videoMode->timing = NULL;
588 if (useTiming && mode->timing != NULL) {
590 regs.es = ADDRESS_SEGMENT(mode->timing);
591 regs.edi = ADDRESS_OFFSET(mode->timing);
852 // timing issue between getting the EDID data and setting the video
857 if ((sMode->timing == NULL || vesa_set_mode(sMode, true) != B_OK)