Lines Matching refs:t4

376 #define LP4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn) \
381 t4 _##name##_v4 = (v4); \
391 register t4 _n4 __asm(#r4) = _##name##_v4; \
400 #define LP4NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn) \
405 t4 _##name##_v4 = (v4); \
415 register t4 _n4 __asm(#r4) = _##name##_v4; \
424 #define LP4FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn, fpt) \
430 t4 _##name##_v4 = (v4); \
440 register t4 _n4 __asm(#r4) = _##name##_v4; \
449 #define LP5(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \
454 t4 _##name##_v4 = (v4); \
465 register t4 _n4 __asm(#r4) = _##name##_v4; \
475 #define LP5NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \
480 t4 _##name##_v4 = (v4); \
491 register t4 _n4 __asm(#r4) = _##name##_v4; \
501 #define LP5FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn, fpt) \
507 t4 _##name##_v4 = (v4); \
518 register t4 _n4 __asm(#r4) = _##name##_v4; \
529 #define LP5A4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \
534 t4 _##name##_v4 = (v4); \
545 register t4 _n4 __asm(#r4) = _##name##_v4; \
555 #define LP6(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn) \
560 t4 _##name##_v4 = (v4); \
572 register t4 _n4 __asm(#r4) = _##name##_v4; \
583 #define LP6NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn) \
588 t4 _##name##_v4 = (v4); \
600 register t4 _n4 __asm(#r4) = _##name##_v4; \
610 #define LP7(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \
615 t4 _##name##_v4 = (v4); \
628 register t4 _n4 __asm(#r4) = _##name##_v4; \
640 #define LP7NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \
645 t4 _##name##_v4 = (v4); \
658 register t4 _n4 __asm(#r4) = _##name##_v4; \
670 #define LP7A4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \
675 t4 _##name##_v4 = (v4); \
688 register t4 _n4 __asm(#r4) = _##name##_v4; \
704 #define LP8(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, bt, bn) \
709 t4 _##name##_v4 = (v4); \
723 register t4 _n4 __asm(#r4) = _##name##_v4; \
737 #define LP8NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, bt, bn) \
742 t4 _##name##_v4 = (v4); \
756 register t4 _n4 __asm(#r4) = _##name##_v4; \
769 #define LP9(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, bt, bn) \
774 t4 _##name##_v4 = (v4); \
789 register t4 _n4 __asm(#r4) = _##name##_v4; \
804 #define LP9NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, bt, bn) \
809 t4 _##name##_v4 = (v4); \
824 register t4 _n4 __asm(#r4) = _##name##_v4; \
838 #define LP10(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, bt, bn) \
843 t4 _##name##_v4 = (v4); \
859 register t4 _n4 __asm(#r4) = _##name##_v4; \
875 #define LP10NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, bt, bn) \
880 t4 _##name##_v4 = (v4); \
896 register t4 _n4 __asm(#r4) = _##name##_v4; \
911 #define LP11(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, t11, v11, r11, bt, bn) \
916 t4 _##name##_v4 = (v4); \
933 register t4 _n4 __asm(#r4) = _##name##_v4; \