platform/amiga_m68k/rom_calls.h

162 #define LP2(offs, rt, name, t1, v1, r1, t2, v2, r2, bt, bn)	\
165    t2 _##name##_v2 = (v2);					\
173       register t2 _n2 __asm(#r2) = _##name##_v2;		\
182 #define LP2NR(offs, name, t1, v1, r1, t2, v2, r2, bt, bn)	\
185    t2 _##name##_v2 = (v2);					\
193       register t2 _n2 __asm(#r2) = _##name##_v2;		\
202 #define LP2UB(offs, rt, name, t1, v1, r1, t2, v2, r2)		\
205    t2 _##name##_v2 = (v2);					\
212       register t2 _n2 __asm(#r2) = _##name##_v2;		\
222 #define LP2FP(offs, rt, name, t1, v1, r1, t2, v2, r2, bt, bn, fpt) \
226    t2 _##name##_v2 = (v2);					\
234       register t2 _n2 __asm(#r2) = _##name##_v2;		\
243 #define LP3(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn) \
246    t2 _##name##_v2 = (v2);					\
255       register t2 _n2 __asm(#r2) = _##name##_v2;		\
265 #define LP3NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn) \
268    t2 _##name##_v2 = (v2);					\
277       register t2 _n2 __asm(#r2) = _##name##_v2;		\
287 #define LP3UB(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3) \
290    t2 _##name##_v2 = (v2);					\
298       register t2 _n2 __asm(#r2) = _##name##_v2;		\
309 #define LP3NRUB(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3)	\
312    t2 _##name##_v2 = (v2);					\
320       register t2 _n2 __asm(#r2) = _##name##_v2;		\
330 #define LP3FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn, fpt) \
334    t2 _##name##_v2 = (v2);					\
343       register t2 _n2 __asm(#r2) = _##name##_v2;		\
354 #define LP3NRFP(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn, fpt) \
358    t2 _##name##_v2 = (v2);					\
367       register t2 _n2 __asm(#r2) = _##name##_v2;		\
376 #define LP4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn) \
379    t2 _##name##_v2 = (v2);					\
389       register t2 _n2 __asm(#r2) = _##name##_v2;		\
400 #define LP4NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn) \
403    t2 _##name##_v2 = (v2);					\
413       register t2 _n2 __asm(#r2) = _##name##_v2;		\
424 #define LP4FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn, fpt) \
428    t2 _##name##_v2 = (v2);					\
438       register t2 _n2 __asm(#r2) = _##name##_v2;		\
449 #define LP5(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \
452    t2 _##name##_v2 = (v2);					\
463       register t2 _n2 __asm(#r2) = _##name##_v2;		\
475 #define LP5NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \
478    t2 _##name##_v2 = (v2);					\
489       register t2 _n2 __asm(#r2) = _##name##_v2;		\
501 #define LP5FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn, fpt) \
505    t2 _##name##_v2 = (v2);					\
516       register t2 _n2 __asm(#r2) = _##name##_v2;		\
529 #define LP5A4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \
532    t2 _##name##_v2 = (v2);					\
543       register t2 _n2 __asm(#r2) = _##name##_v2;		\
555 #define LP6(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn) \
558    t2 _##name##_v2 = (v2);					\
570       register t2 _n2 __asm(#r2) = _##name##_v2;		\
583 #define LP6NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn) \
586    t2 _##name##_v2 = (v2);					\
598       register t2 _n2 __asm(#r2) = _##name##_v2;		\
610 #define LP7(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \
613    t2 _##name##_v2 = (v2);					\
626       register t2 _n2 __asm(#r2) = _##name##_v2;		\
640 #define LP7NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \
643    t2 _##name##_v2 = (v2);					\
656       register t2 _n2 __asm(#r2) = _##name##_v2;		\
670 #define LP7A4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \
673    t2 _##name##_v2 = (v2);					\
686       register t2 _n2 __asm(#r2) = _##name##_v2;		\
704 #define LP8(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, bt, bn) \
707    t2 _##name##_v2 = (v2);					\
721       register t2 _n2 __asm(#r2) = _##name##_v2;		\
737 #define LP8NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, bt, bn) \
740    t2 _##name##_v2 = (v2);					\
754       register t2 _n2 __asm(#r2) = _##name##_v2;		\
769 #define LP9(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, bt, bn) \
772    t2 _##name##_v2 = (v2);					\
787       register t2 _n2 __asm(#r2) = _##name##_v2;		\
804 #define LP9NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, bt, bn) \
807    t2 _##name##_v2 = (v2);					\
822       register t2 _n2 __asm(#r2) = _##name##_v2;		\
838 #define LP10(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, bt, bn) \
841    t2 _##name##_v2 = (v2);					\
857       register t2 _n2 __asm(#r2) = _##name##_v2;		\
875 #define LP10NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, bt, bn) \
878    t2 _##name##_v2 = (v2);					\
894       register t2 _n2 __asm(#r2) = _##name##_v2;		\
911 #define LP11(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, t11, v11, r11, bt, bn) \
914    t2 _##name##_v2 = (v2);					\
931       register t2 _n2 __asm(#r2) = _##name##_v2;		\