rtwn/rtl8821a/r21a_init.c

65 r21a_power_on(struct rtwn_softc *sc)
74 	RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
78 	RTWN_CHK(rtwn_setbits_1(sc, R92C_GPIO_INTM + 2, 0x01, 0));
81 	RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
85 	RTWN_CHK(rtwn_setbits_1(sc, R92C_LDOA15_CTRL, 0, R92C_LDOA15_CTRL_EN));
88 	RTWN_CHK(rtwn_setbits_1(sc, 0x067, 0x10, 0));
91 	rtwn_delay(sc, 1000);
94 	RTWN_CHK(rtwn_setbits_1(sc, R92C_SYS_ISO_CTRL,
98 	RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
105 		if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
107 		rtwn_delay(sc, 10);
110 		device_printf(sc->sc_dev,
116 	RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
120 	RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
124 	RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
127 	RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
130 		if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
133 		rtwn_delay(sc, 10);
139 	RTWN_CHK(rtwn_setbits_1(sc, R92C_LEDCFG3, 0, 0x01));
142 	RTWN_CHK(rtwn_setbits_1(sc, 0x067, 0, 0x30));
144 	RTWN_CHK(rtwn_setbits_1(sc, 0x025, 0x40, 0));
147 	RTWN_CHK(rtwn_setbits_1(sc, R92C_GPIO_INTM + 1, 0, 0x02));
150 	RTWN_CHK(rtwn_setbits_1(sc, 0x063, 0, 0x02));
153 	RTWN_CHK(rtwn_setbits_1(sc, 0x062, 0x02, 0));
156 	RTWN_CHK(rtwn_setbits_1(sc, R92C_HSIMR, 0, 0x01));
159 	RTWN_CHK(rtwn_setbits_1(sc, R92C_HSIMR + 2, 0, 0x02));
162 	RTWN_CHK(rtwn_setbits_1(sc, R92C_APE_PLL_CTRL_EXT + 2, 0xFF, 0x82));
164 	RTWN_CHK(rtwn_setbits_1(sc, R92C_AFE_MISC, 0, 0x40));
167 	RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0x0000));
168 	RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
172 	    ((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) |
175 	if (rtwn_read_4(sc, R92C_SYS_CFG) & R92C_SYS_CFG_TRP_BT_EN)
176 		RTWN_CHK(rtwn_setbits_1(sc, R92C_LDO_SWR_CTRL, 0, 0x40));
183 r21a_power_off(struct rtwn_softc *sc)
185 	struct r12a_softc *rs = sc->sc_priv;
189 	error = rtwn_write_1(sc, R92C_CR, 0);
195 	rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
199 		if (rtwn_read_4(sc, R88E_SCH_TXCMD) == 0)
202 		rtwn_delay(sc, 5000);
205 		device_printf(sc->sc_dev, "%s: failed to block Tx queues\n",
211 	rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BBRSTB, 0);
213 	rtwn_delay(sc, 1);
216 	rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BB_GLB_RST, 0);
219 	rtwn_write_1(sc, R92C_CR,
223 	rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1);
226 	rtwn_setbits_1(sc, R92C_DUAL_TSF_RST, 0, R92C_DUAL_TSF_RST_TXOK);
230 	if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL)
231 		r21a_fw_reset(sc, RTWN_FW_RESET_SHUTDOWN);
235 	rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_CPUEN,
237 	rtwn_write_1(sc, R92C_MCUFWDL, 0);
241 	rtwn_write_1(sc, R92C_RF_CTRL, 0);
243 	rtwn_setbits_1(sc, R92C_LEDCFG3, 0x01, 0);
246 	rtwn_setbits_1(sc, R92C_GPIO_INTM + 1, 0x02, 0);
249 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
253 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_APFM_OFF,
257 		if ((rtwn_read_2(sc, R92C_APS_FSMCO) &
261 		rtwn_delay(sc, 5000);
264 		device_printf(sc->sc_dev, "%s: could not turn off MAC\n",
270 	rtwn_setbits_1(sc, R92C_SYS_ISO_CTRL, 0, R92C_SYS_ISO_CTRL_IP2MAC);
273 	rtwn_setbits_1(sc, R92C_LDOA15_CTRL, R92C_LDOA15_CTRL_EN, 0);
276 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_AFSM_PCIE,
280 	rtwn_setbits_1(sc, R92C_GPIO_INTM + 2, 0, 0x01);
286 r21a_check_condition(struct rtwn_softc *sc, const uint8_t cond[])
288 	struct r12a_softc *rs = sc->sc_priv;
292 	RTWN_DPRINTF(sc, RTWN_DEBUG_RESET,
321 r21a_crystalcap_write(struct rtwn_softc *sc)
323 	struct r12a_softc *rs = sc->sc_priv;
328 	reg = rtwn_bb_read(sc, R92C_MAC_PHY_CTRL);
330 	rtwn_bb_write(sc, R92C_MAC_PHY_CTRL, reg);
334 r21a_init_bcnq1_boundary(struct rtwn_softc *sc)
340 	RTWN_CHK(rtwn_write_1(sc, R88E_TXPKTBUF_BCNQ1_BDNY,
342 	RTWN_CHK(rtwn_write_1(sc, R21A_DWBCN1_CTRL + 1,
344 	RTWN_CHK(rtwn_setbits_1_shift(sc, R21A_DWBCN1_CTRL, 0,
352 r21a_init_ampdu_fwhw(struct rtwn_softc *sc)
354 	rtwn_write_1(sc, R92C_FWHW_TXQ_CTRL,
356 	rtwn_write_4(sc, R92C_FAST_EDCA_CTRL, 0x03087777);