rtwn/rtl8821a/r21a_init.c

67 #define RTWN_CHK(res) do {	\
74 	RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
78 	RTWN_CHK(rtwn_setbits_1(sc, R92C_GPIO_INTM + 2, 0x01, 0));
81 	RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
85 	RTWN_CHK(rtwn_setbits_1(sc, R92C_LDOA15_CTRL, 0, R92C_LDOA15_CTRL_EN));
88 	RTWN_CHK(rtwn_setbits_1(sc, 0x067, 0x10, 0));
94 	RTWN_CHK(rtwn_setbits_1(sc, R92C_SYS_ISO_CTRL,
98 	RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
116 	RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
120 	RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
124 	RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
127 	RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
139 	RTWN_CHK(rtwn_setbits_1(sc, R92C_LEDCFG3, 0, 0x01));
142 	RTWN_CHK(rtwn_setbits_1(sc, 0x067, 0, 0x30));
144 	RTWN_CHK(rtwn_setbits_1(sc, 0x025, 0x40, 0));
147 	RTWN_CHK(rtwn_setbits_1(sc, R92C_GPIO_INTM + 1, 0, 0x02));
150 	RTWN_CHK(rtwn_setbits_1(sc, 0x063, 0, 0x02));
153 	RTWN_CHK(rtwn_setbits_1(sc, 0x062, 0x02, 0));
156 	RTWN_CHK(rtwn_setbits_1(sc, R92C_HSIMR, 0, 0x01));
159 	RTWN_CHK(rtwn_setbits_1(sc, R92C_HSIMR + 2, 0, 0x02));
162 	RTWN_CHK(rtwn_setbits_1(sc, R92C_APE_PLL_CTRL_EXT + 2, 0xFF, 0x82));
164 	RTWN_CHK(rtwn_setbits_1(sc, R92C_AFE_MISC, 0, 0x40));
167 	RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0x0000));
168 	RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
176 		RTWN_CHK(rtwn_setbits_1(sc, R92C_LDO_SWR_CTRL, 0, 0x40));
179 #undef RTWN_CHK
336 #define RTWN_CHK(res) do {	\
340 	RTWN_CHK(rtwn_write_1(sc, R88E_TXPKTBUF_BCNQ1_BDNY,
342 	RTWN_CHK(rtwn_write_1(sc, R21A_DWBCN1_CTRL + 1,
344 	RTWN_CHK(rtwn_setbits_1_shift(sc, R21A_DWBCN1_CTRL, 0,
348 #undef RTWN_CHK