rtwn/rtl8812a/r12a_init.c

66 r12a_check_condition(struct rtwn_softc *sc, const uint8_t cond[])
68 	struct r12a_softc *rs = sc->sc_priv;
72 	RTWN_DPRINTF(sc, RTWN_DEBUG_RESET,
115 r12a_set_page_size(struct rtwn_softc *sc)
117 	return (rtwn_setbits_1(sc, R92C_PBP, R92C_PBP_PSTX_M,
122 r12a_init_edca(struct rtwn_softc *sc)
124 	r92c_init_edca(sc);
127 	rtwn_write_1(sc, R92C_USTIME_TSF, 0x50);
128 	rtwn_write_1(sc, R92C_USTIME_EDCA, 0x50);
132 r12a_init_bb(struct rtwn_softc *sc)
136 	rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, 0, R92C_SYS_FUNC_EN_USBA);
139 	rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, 0,
143 	rtwn_write_1(sc, R92C_RF_CTRL,
147 	rtwn_write_1(sc, R12A_RF_B_CTRL,
151 	for (i = 0; i < sc->bb_size; i++) {
152 		const struct rtwn_bb_prog *bb_prog = &sc->bb_prog[i];
154 		while (!rtwn_check_condition(sc, bb_prog->cond)) {
162 			RTWN_DPRINTF(sc, RTWN_DEBUG_RESET,
166 			rtwn_bb_write(sc, bb_prog->reg[j], bb_prog->val[j]);
167 			rtwn_delay(sc, 1);
174 	for (i = 0; i < sc->agc_size; i++) {
175 		const struct rtwn_agc_prog *agc_prog = &sc->agc_prog[i];
177 		while (!rtwn_check_condition(sc, agc_prog->cond)) {
185 			RTWN_DPRINTF(sc, RTWN_DEBUG_RESET,
188 			rtwn_bb_write(sc, 0x81c, agc_prog->val[j]);
189 			rtwn_delay(sc, 1);
193 	for (i = 0; i < sc->nrxchains; i++) {
194 		rtwn_bb_write(sc, R12A_INITIAL_GAIN(i), 0x22);
195 		rtwn_delay(sc, 1);
196 		rtwn_bb_write(sc, R12A_INITIAL_GAIN(i), 0x20);
197 		rtwn_delay(sc, 1);
200 	rtwn_r12a_crystalcap_write(sc);
202 	if (rtwn_bb_read(sc, R12A_CCK_RPT_FORMAT) & R12A_CCK_RPT_FORMAT_HIPWR)
203 		sc->sc_flags |= RTWN_FLAG_CCK_HIPWR;
207 r12a_init_rf(struct rtwn_softc *sc)
211 	for (chain = 0, i = 0; chain < sc->nrxchains; chain++, i++) {
213 		i += r92c_init_rf_chain(sc, &sc->rf_prog[i], chain);
218 r12a_crystalcap_write(struct rtwn_softc *sc)
220 	struct r12a_softc *rs = sc->sc_priv;
225 	reg = rtwn_bb_read(sc, R92C_MAC_PHY_CTRL);
227 	rtwn_bb_write(sc, R92C_MAC_PHY_CTRL, reg);
231 r12a_rf_init_workaround(struct rtwn_softc *sc)
234 	rtwn_write_1(sc, R92C_RF_CTRL,
236 	rtwn_write_1(sc, R92C_RF_CTRL,
239 	rtwn_write_1(sc, R12A_RF_B_CTRL,
241 	rtwn_write_1(sc, R12A_RF_B_CTRL,
247 r12a_power_on(struct rtwn_softc *sc)
255 	r12a_rf_init_workaround(sc);
258 	RTWN_CHK(rtwn_setbits_1(sc, R92C_SPS0_CTRL + 1, 0, 0x01));
261 	RTWN_CHK(rtwn_setbits_2(sc, 0x014, 0x0180, 0));
264 	RTWN_CHK(rtwn_setbits_1(sc, R92C_LPLDO_CTRL, R92C_LPLDO_CTRL_SLEEP,
268 	RTWN_CHK(rtwn_write_1(sc, R92C_GPIO_IOSEL, 0));
271 	RTWN_CHK(rtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 0));
274 	RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
278 	RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN,
282 	RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
287 		if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
289 		rtwn_delay(sc, 10);
292 		device_printf(sc->sc_dev,
298 	RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
301 	RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
304 		if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
307 		rtwn_delay(sc, 10);
313 	RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0x0000));
314 	RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
318 	    ((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) |
325 r12a_power_off(struct rtwn_softc *sc)
327 	struct r12a_softc *rs = sc->sc_priv;
331 	error = rtwn_write_1(sc, R92C_CR, 0);
337 	rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
341 		if (rtwn_read_4(sc, R88E_SCH_TXCMD) == 0)
344 		rtwn_delay(sc, 5000);
347 		device_printf(sc->sc_dev, "%s: failed to block Tx queues\n",
353 	rtwn_write_1(sc, R12A_HSSI_PARAM1(0), 0x04);
354 	rtwn_write_1(sc, R12A_HSSI_PARAM1(1), 0x04);
357 	rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BBRSTB, 0);
359 	rtwn_delay(sc, 1);
362 	rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BB_GLB_RST, 0);
365 	rtwn_write_1(sc, R92C_CR,
369 	rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1);
372 	rtwn_setbits_1(sc, R92C_DUAL_TSF_RST, 0, R92C_DUAL_TSF_RST_TXOK);
376 	if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL)
377 		r12a_fw_reset(sc, RTWN_FW_RESET_SHUTDOWN);
381 	rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_CPUEN,
383 	rtwn_write_1(sc, R92C_MCUFWDL, 0);
387 	rtwn_write_1(sc, R12A_HSSI_PARAM1(0), 0x04);
388 	rtwn_write_1(sc, R12A_HSSI_PARAM1(1), 0x04);
391 	rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BB_GLB_RST, 0);
393 	rtwn_delay(sc, 1);
396 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0xff,
400 	rtwn_setbits_1(sc, R92C_SYS_CLKR, R92C_SYS_CLKR_ANA8M, 0);
403 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_APFM_OFF,
407 		if ((rtwn_read_2(sc, R92C_APS_FSMCO) &
411 		rtwn_delay(sc, 5000);
414 		device_printf(sc->sc_dev, "%s: could not turn off MAC\n",
420 	rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_CPUEN,
424 	rtwn_write_1(sc, R92C_MCUFWDL,
427 	rtwn_setbits_1(sc, R92C_GPIO_IO_SEL, 0xf0, 0xc0);
430 	rtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 0x07);
433 	rtwn_write_1(sc, R92C_GPIO_OUT, 0);
436 	rtwn_write_1(sc, R92C_GPIO_IOSEL, 0xff);
438 	rtwn_write_1(sc, R92C_GPIO_MOD, 0);
441 	rtwn_setbits_2(sc, 0x014, 0, 0x0180);
444 	rtwn_setbits_1(sc, R92C_SPS0_CTRL + 1, 0x01, 0);
447 	rtwn_setbits_1(sc, R92C_LPLDO_CTRL, 0, R92C_LPLDO_CTRL_SLEEP);
450 	rtwn_setbits_1(sc, R92C_SYS_CLKR, R92C_SYS_CLKR_ANA8M, 0);
453 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0xff,
457 	rtwn_setbits_1(sc, R92C_RF_CTRL, R92C_RF_CTRL_RSTB, 0);
460 	rtwn_setbits_1(sc, R12A_RF_B_CTRL, R92C_RF_CTRL_RSTB, 0);
463 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_AFSM_HSUS,
470 r12a_init_intr(struct rtwn_softc *sc)
472 	rtwn_write_4(sc, R88E_HIMR, 0);
473 	rtwn_write_4(sc, R88E_HIMRE, 0);
477 r12a_init_antsel(struct rtwn_softc *sc)
481 	rtwn_write_1(sc, R92C_LEDCFG2, 0x82);
482 	rtwn_bb_setbits(sc, R92C_FPGA0_RFPARAM(0), 0, 0x2000);
483 	reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(0));
484 	sc->sc_ant = MS(reg, R92C_FPGA0_RFIFACEOE0_ANT);