Lines Matching refs:sc
65 r12a_write_txpower(struct rtwn_softc *sc, int chain,
71 rtwn_bb_write(sc, R12A_TXAGC_CCK11_1(chain),
79 rtwn_bb_write(sc, R12A_TXAGC_OFDM18_6(chain),
84 rtwn_bb_write(sc, R12A_TXAGC_OFDM54_24(chain),
90 rtwn_bb_write(sc, R12A_TXAGC_MCS3_0(chain),
95 rtwn_bb_write(sc, R12A_TXAGC_MCS7_4(chain),
100 if (sc->ntxchains >= 2) {
101 rtwn_bb_write(sc, R12A_TXAGC_MCS11_8(chain),
106 rtwn_bb_write(sc, R12A_TXAGC_MCS15_12(chain),
117 r12a_get_power_group(struct rtwn_softc *sc, struct ieee80211_channel *c)
164 r12a_get_txpower(struct rtwn_softc *sc, int chain,
167 struct r12a_softc *rs = sc->sc_priv;
171 group = r12a_get_power_group(sc, c);
173 device_printf(sc->sc_dev, "%s: incorrect channel\n", __func__);
178 max_mcs = RTWN_RIDX_HT_MCS(sc->ntxchains * 8 - 1);
192 for (i = 0; i < sc->ntxchains; i++) {
218 for (i = 0; i < sc->ntxchains; i++) {
246 if (sc->sc_debug & RTWN_DEBUG_TXPWR) {
256 r12a_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c)
261 for (i = 0; i < sc->ntxchains; i++) {
264 r12a_get_txpower(sc, i, c, power);
266 r12a_write_txpower(sc, i, c, power);
271 r12a_fix_spur(struct rtwn_softc *sc, struct ieee80211_channel *c)
273 struct r12a_softc *rs = sc->sc_priv;
278 rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0xc00);
279 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0, 0x40000000);
281 rtwn_bb_setbits(sc, R12A_RFMOD, 0x400, 0x800);
285 rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0x300);
286 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK,
289 rtwn_bb_setbits(sc, R12A_RFMOD, 0x100, 0x200);
290 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK,
298 rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0x300);
300 rtwn_bb_setbits(sc, R12A_RFMOD, 0x100, 0x200);
305 r12a_set_band(struct rtwn_softc *sc, struct ieee80211_channel *c)
307 struct ieee80211com *ic = &sc->sc_ic;
308 struct r12a_softc *rs = sc->sc_priv;
314 if ((sc->sc_flags & (RTWN_STARTED | RTWN_RUNNING)) !=
316 !(rtwn_read_1(sc, R12A_CCK_CHECK) & R12A_CCK_CHECK_5GHZ))
319 rtwn_get_rates(sc, ieee80211_get_suprates(ic, c), NULL, &basicrates,
322 rtwn_r12a_set_band_2ghz(sc, basicrates);
325 rtwn_r12a_set_band_5ghz(sc, basicrates);
351 rtwn_bb_setbits(sc, R12A_TX_SCALE(i), R12A_TX_SCALE_SWING_M,
357 r12a_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c)
363 r12a_set_band(sc, c);
377 rtwn_bb_setbits(sc, R12A_FC_AREA, 0x1ffe0000, val);
379 for (i = 0; i < sc->nrxchains; i++) {
389 rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW, 0x70300, val);
392 rtwn_r12a_fix_spur(sc, c);
395 rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW, 0xff, chan);
400 rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x80, 0x100);
415 rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x100, 0x80);
416 rtwn_write_1(sc, R12A_DATA_SEC, ext_chan);
418 rtwn_bb_setbits(sc, R12A_RFMOD, 0x003003c3, 0x00300201);
419 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0x40000000, 0);
422 val = rtwn_bb_read(sc, R12A_RFMOD);
424 rtwn_bb_write(sc, R12A_RFMOD, val);
426 val = rtwn_bb_read(sc, R12A_CCA_ON_SEC);
428 rtwn_bb_write(sc, R12A_CCA_ON_SEC, val);
430 if (rtwn_read_1(sc, 0x837) & 0x04)
432 else if (sc->nrxchains == 2 && sc->ntxchains == 2)
437 rtwn_bb_setbits(sc, R12A_L1_PEAK_TH, 0x03c00000, val);
440 rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM, 0x10, 0);
442 rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM, 0, 0x10);
446 rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x180, 0);
447 rtwn_write_1(sc, R12A_DATA_SEC, R12A_DATA_SEC_NO_EXT);
449 rtwn_bb_setbits(sc, R12A_RFMOD, 0x003003c3, 0x00300200);
450 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0x40000000, 0);
452 if (sc->nrxchains == 2 && sc->ntxchains == 2)
457 rtwn_bb_setbits(sc, R12A_L1_PEAK_TH, 0x03c00000, val);
463 rtwn_r12a_fix_spur(sc, c);
465 for (i = 0; i < sc->nrxchains; i++)
466 rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW, 0xc00, val);
469 r12a_set_txpower(sc, c);
473 r12a_set_band_2ghz(struct rtwn_softc *sc, uint32_t basicrates)
475 struct r12a_softc *rs = sc->sc_priv;
478 rtwn_bb_setbits(sc, R12A_OFDMCCK_EN,
481 rtwn_bb_setbits(sc, R12A_BW_INDICATION, 0x02, 0x01);
482 rtwn_bb_setbits(sc, R12A_PWED_TH, 0x3e000, 0x2e000);
485 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x03, 0);
491 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77777777);
492 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77777777);
493 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0);
494 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0);
497 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x54337770);
498 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x54337770);
499 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000);
500 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000);
501 rtwn_bb_setbits(sc, R12A_ANTSEL_SW, 0x0303, 0x01);
504 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77777777);
505 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77777777);
506 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x00100000);
507 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x00100000);
510 rtwn_write_1(sc, R12A_RFE_PINMUX(0) + 2, 0x77);
511 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77777777);
512 rtwn_setbits_1(sc, R12A_RFE_INV(0) + 3, 0x01, 0);
513 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0);
519 rtwn_bb_setbits(sc, R12A_TX_PATH, 0xf0, 0x10);
520 rtwn_bb_setbits(sc, R12A_CCK_RX_PATH, 0x0f000000, 0x01000000);
523 rtwn_set_basicrates(sc, basicrates);
525 rtwn_write_1(sc, R12A_CCK_CHECK, 0);
529 r12a_set_band_5ghz(struct rtwn_softc *sc, uint32_t basicrates)
531 struct r12a_softc *rs = sc->sc_priv;
534 rtwn_write_1(sc, R12A_CCK_CHECK, R12A_CCK_CHECK_5GHZ);
537 if ((rtwn_read_2(sc, R12A_TXPKT_EMPTY) & 0x30) == 0x30)
540 rtwn_delay(sc, 25);
543 device_printf(sc->sc_dev,
545 __func__, rtwn_read_2(sc, R12A_TXPKT_EMPTY));
549 rtwn_bb_setbits(sc, R12A_OFDMCCK_EN, R12A_OFDMCCK_EN_CCK,
552 rtwn_bb_setbits(sc, R12A_BW_INDICATION, 0x01, 0x02);
553 rtwn_bb_setbits(sc, R12A_PWED_TH, 0x3e000, 0x2a000);
556 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x03, 0x01);
560 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77337717);
561 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337717);
562 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000);
563 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000);
566 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77337717);
567 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337717);
568 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0);
569 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0);
573 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77337777);
574 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337777);
575 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000);
576 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000);
579 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x54337717);
580 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x54337717);
581 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000);
582 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000);
583 rtwn_bb_setbits(sc, R12A_ANTSEL_SW, 0x0303, 0x01);
586 rtwn_write_1(sc, R12A_RFE_PINMUX(0) + 2, 0x33);
587 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337777);
588 rtwn_setbits_1(sc, R12A_RFE_INV(0) + 3, 0, 0x01);
589 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000);
595 rtwn_bb_setbits(sc, R12A_TX_PATH, 0xf0, 0);
596 rtwn_bb_setbits(sc, R12A_CCK_RX_PATH, 0, 0x0f000000);
599 rtwn_set_basicrates(sc, basicrates);