rtwn/rtl8192e/r92e_init.c

66 r92e_llt_init(struct rtwn_softc *sc)
70 	error = rtwn_setbits_4(sc, R92C_AUTO_LLT, 0, R92C_AUTO_LLT_INIT);
74 		if (!(rtwn_read_4(sc, R92C_AUTO_LLT) & R92C_AUTO_LLT_INIT))
76 		rtwn_delay(sc, 1);
82 r92e_crystalcap_write(struct rtwn_softc *sc)
84 	struct r92e_softc *rs = sc->sc_priv;
89 	reg = rtwn_bb_read(sc, R92E_AFE_XTAL_CTRL);
90 	rtwn_bb_write(sc, R92E_AFE_XTAL_CTRL,
92 	rtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 0x000f81fb);
96 r92e_init_bb(struct rtwn_softc *sc)
100 	rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0,
104 	rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0,
109 	rtwn_write_1(sc, R92C_RF_CTRL,
113 	for (i = 0; i < sc->bb_size; i++) {
114 		const struct rtwn_bb_prog *bb_prog = &sc->bb_prog[i];
116 		while (!rtwn_check_condition(sc, bb_prog->cond)) {
124 			RTWN_DPRINTF(sc, RTWN_DEBUG_RESET,
128 			rtwn_bb_write(sc, bb_prog->reg[j], bb_prog->val[j]);
129 			rtwn_delay(sc, 1);
134 	for (i = 0; i < sc->agc_size; i++) {
135 		const struct rtwn_agc_prog *agc_prog = &sc->agc_prog[i];
137 		while (!rtwn_check_condition(sc, agc_prog->cond)) {
145 			RTWN_DPRINTF(sc, RTWN_DEBUG_RESET,
148 			rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE,
150 			rtwn_delay(sc, 1);
154 	if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & R92C_HSSI_PARAM2_CCK_HIPWR)
155 		sc->sc_flags |= RTWN_FLAG_CCK_HIPWR;
157 	rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x00040022);
158 	rtwn_delay(sc, 1);
159 	rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x00040020);
160 	rtwn_delay(sc, 1);
162 	r92e_crystalcap_write(sc);
166 r92e_init_rf(struct rtwn_softc *sc)
168 	struct r92e_softc *rs = sc->sc_priv;
172 	for (chain = 0, i = 0; chain < sc->nrxchains; chain++, i++) {
176 		reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
180 		rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(chain),
182 		rtwn_delay(sc, 1);
184 		rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(chain),
186 		rtwn_delay(sc, 1);
188 		rtwn_bb_setbits(sc, R92C_HSSI_PARAM2(chain),
190 		rtwn_delay(sc, 1);
191 		rtwn_bb_setbits(sc, R92C_HSSI_PARAM2(chain),
193 		rtwn_delay(sc, 1);
196 		i += r92c_init_rf_chain(sc, &sc->rf_prog[i], chain);
199 		rs->rf_chnlbw[chain] = rtwn_rf_read(sc, chain, R92C_RF_CHNLBW);
203 	rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_CCK_EN);
204 	rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_OFDM_EN);
208 r92e_adj_crystal(struct rtwn_softc *sc)
211 	rtwn_setbits_1(sc, R92C_AFE_PLL_CTRL, R92C_AFE_PLL_CTRL_FREF_SEL, 0);
212 	rtwn_setbits_4(sc, R92E_APE_PLL_CTRL_EXT, 0x00000380, 0);
213 	rtwn_setbits_1(sc, R92C_AFE_PLL_CTRL, 0x40, 0);
214 	rtwn_setbits_4(sc, R92E_APE_PLL_CTRL_EXT, 0x00200000, 0);
218 r92e_power_on(struct rtwn_softc *sc)
226 	if (rtwn_read_4(sc, R92C_SYS_CFG) & R92C_SYS_CFG_TRP_BT_EN)
227 		RTWN_CHK(rtwn_write_1(sc, R92C_LDO_SWR_CTRL, 0xc3));
229 		RTWN_CHK(rtwn_setbits_4(sc, R92E_LDOV12_CTRL, 0x00100000,
231 		RTWN_CHK(rtwn_write_1(sc, R92C_LDO_SWR_CTRL, 0x83));
234 	r92e_adj_crystal(sc);
237 	RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
241 	RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
247 		if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
249 		rtwn_delay(sc, 10);
252 		device_printf(sc->sc_dev,
258 	RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
261 	RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
264 		if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
267 		rtwn_delay(sc, 10);
273 	RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0));
274 	RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
278 	    ((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) |
285 r92e_power_off(struct rtwn_softc *sc)
290 	error = rtwn_write_1(sc, R92C_CR, 0);
296 	rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
300 		if (rtwn_read_4(sc, R88E_SCH_TXCMD) == 0)
303 		rtwn_delay(sc, 10);
306 		device_printf(sc->sc_dev, "%s: failed to block Tx queues\n",
312 	rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BBRSTB, 0);
314 	rtwn_delay(sc, 1);
317 	rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BB_GLB_RST, 0);
320 	rtwn_write_1(sc, R92C_CR,
324 	rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1);
327 	rtwn_setbits_1(sc, R92C_DUAL_TSF_RST, 0, R92C_DUAL_TSF_RST_TXOK);
330 	rtwn_write_1(sc, R92C_MCUFWDL, 0);
334 	rtwn_setbits_1(sc, R92C_RSV_CTRL + 1, 0x01, 0);
336 	rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN,
340 	rtwn_setbits_1(sc, R92C_RSV_CTRL + 1, 0, 0x01);
345 	rtwn_write_1(sc, R92C_RF_CTRL, 0);
348 	rtwn_setbits_1(sc, R92C_LEDCFG2, 0x80, 0);
351 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_APFM_OFF,
356 		if ((rtwn_read_2(sc, R92C_APS_FSMCO) &
360 		rtwn_delay(sc, 10);
363 		device_printf(sc->sc_dev, "%s: could not turn off MAC\n",
369 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0xff,
373 	rtwn_setbits_1(sc, 0xcc, 0, 0x4);
376 	rtwn_setbits_1(sc, R92C_SPS0_CTRL, 0x1, 0);
379 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_AFSM_PCIE,
383 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,