rtl8192c/pci/r92ce_init.c

61 r92ce_init_intr(struct rtwn_softc *sc)
64 	rtwn_write_4(sc, R92C_HISR, 0x00000000);
65 	rtwn_write_4(sc, R92C_HIMR, 0x00000000);
69 r92ce_init_edca(struct rtwn_softc *sc)
72 	rtwn_write_2(sc, R92C_SPEC_SIFS, 0x1010);
73 	rtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x1010);
74 	rtwn_write_2(sc, R92C_SIFS_CCK, 0x1010);
75 	rtwn_write_2(sc, R92C_SIFS_OFDM, 0x0e0e);
77 	rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b);
78 	rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f);
79 	rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4322);
80 	rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3222);
84 r92ce_init_bb(struct rtwn_softc *sc)
88 	rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0,
92 	rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83);
94 	rtwn_write_1(sc, R92C_RF_CTRL,
97 	rtwn_write_1(sc, R92C_SYS_FUNC_EN,
102 	rtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80);
104 	rtwn_setbits_4(sc, R92C_LEDCFG0, 0, 0x00800000);
106 	r92c_init_bb_common(sc);
110 r92ce_power_on(struct rtwn_softc *sc)
112 	struct r92c_softc *rs = sc->sc_priv;
118 		if (rtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN)
123 		device_printf(sc->sc_dev,
129 	rtwn_write_1(sc, R92C_RSV_CTRL, 0);
133 		rtwn_setbits_4(sc, R92C_APS_FSMCO, 0,
140 	rtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b);
143 	rtwn_write_1(sc, R92C_AFE_XTAL_CTRL, 0x0f);
149 		rtwn_setbits_4(sc, R92C_AFE_XTAL_CTRL, 0x024800, 0);
152 	rtwn_setbits_2(sc, R92C_SYS_ISO_CTRL, 0xff00,
160 	rtwn_setbits_2(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_APFM_ONMAC);
162 		if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
168 		device_printf(sc->sc_dev, "timeout waiting for MAC auto ON\n");
173 	rtwn_write_2(sc, R92C_APS_FSMCO,
178 	rtwn_setbits_2(sc, R92C_SYS_ISO_CTRL, R92C_SYS_ISO_CTRL_DIOR, 0);
181 		rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x77);
183 		rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x22);
185 	rtwn_write_4(sc, R92C_INT_MIG, 0);
190 		rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0x02, 0);
193 	rtwn_setbits_1(sc, R92C_GPIO_MUXCFG, R92C_GPIO_MUXCFG_RFKILL, 0);
195 	reg = rtwn_read_1(sc, R92C_GPIO_IO_SEL);
197 		device_printf(sc->sc_dev,
204 	rtwn_setbits_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF, 0);
206 		if (!(rtwn_read_1(sc, R92C_APSD_CTRL) &
212 		device_printf(sc->sc_dev,
218 	rtwn_setbits_2(sc, R92C_CR, 0,
222 	    ((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0));
224 	rtwn_write_4(sc, R92C_MCUTST_1, 0x0);
230 r92ce_power_off(struct rtwn_softc *sc)
233 	struct r92c_softc *rs = sc->sc_priv;
244 	rtwn_write_4(sc, R92C_HISR, 0);
245 	rtwn_write_4(sc, R92C_HIMR, 0);
248 	rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
251 	rtwn_write_1(sc, R92C_RF_CTRL, 0);
254 	rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, 0, R92C_SYS_FUNC_EN_BB_GLB_RST);
255 	rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BB_GLB_RST, 0);
258 	rtwn_setbits_2(sc, R92C_CR,
267 	if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL)
268 		r92ce_fw_reset(sc, RTWN_FW_RESET_SHUTDOWN);
272 	rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0x80); /* linux magic number */
273 	rtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); /* ditto */
274 	rtwn_write_1(sc, R92C_AFE_XTAL_CTRL, 0x0e); /* different with btcoex */
275 	rtwn_write_1(sc, R92C_RSV_CTRL, 0x0e);
276 	rtwn_write_1(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_PDN_EN);
280 r92ce_init_ampdu(struct rtwn_softc *sc)
284 	rtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631);	/* MCS7~0 */
285 	rtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16);
289 r92ce_post_init(struct rtwn_softc *sc)
291 	rtwn_write_2(sc, R92C_FWHW_TXQ_CTRL,
294 	rtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff);
297 	r92ce_iq_calib(sc);
299 	r92c_lc_calib(sc);
301 	r92c_pa_bias_init(sc);
304 	rtwn_write_1(sc, 0x15, 0xe9);
307 	if (sc->sc_flags & RTWN_FW_LOADED) {
308 		struct r92c_softc *rs = sc->sc_priv;
310 		if (sc->sc_ratectl_sysctl == RTWN_RATECTL_FW) {
312 			sc->sc_ratectl = RTWN_RATECTL_NET80211;
314 			sc->sc_ratectl = sc->sc_ratectl_sysctl;
318 		    r92c_handle_c2h_report, sc);
321 		sc->sc_ratectl = RTWN_RATECTL_NONE;